Simulation Results: hmac

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.30 %
  • code
  • 97.98 %
  • assert
  • 96.70 %
  • func
  • 43.21 %
  • line
  • 99.69 %
  • branch
  • 99.50 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.230s 130.966us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.730s 30.797us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.650s 71.572us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.880s 1100.195us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.920s 3368.315us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.030s 45.889us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.650s 71.572us 1 1 100.00
hmac_csr_aliasing 6.920s 3368.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 75.950s 1888.890us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 14.940s 1768.875us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.170s 325.709us 1 1 100.00
hmac_test_sha384_vectors 390.880s 11103.194us 1 1 100.00
hmac_test_sha512_vectors 20.460s 875.550us 1 1 100.00
hmac_test_hmac256_vectors 7.160s 758.535us 1 1 100.00
hmac_test_hmac384_vectors 5.590s 151.363us 1 1 100.00
hmac_test_hmac512_vectors 8.700s 282.619us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 3.180s 728.517us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 125.310s 3334.131us 1 1 100.00
error 1 1 100.00
hmac_error 30.490s 18368.376us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 13.500s 988.441us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.230s 130.966us 1 1 100.00
hmac_long_msg 75.950s 1888.890us 1 1 100.00
hmac_back_pressure 14.940s 1768.875us 1 1 100.00
hmac_datapath_stress 125.310s 3334.131us 1 1 100.00
hmac_burst_wr 3.180s 728.517us 1 1 100.00
hmac_stress_all 240.700s 22435.606us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.230s 130.966us 1 1 100.00
hmac_long_msg 75.950s 1888.890us 1 1 100.00
hmac_back_pressure 14.940s 1768.875us 1 1 100.00
hmac_datapath_stress 125.310s 3334.131us 1 1 100.00
hmac_wipe_secret 13.500s 988.441us 1 1 100.00
hmac_test_sha256_vectors 8.170s 325.709us 1 1 100.00
hmac_test_sha384_vectors 390.880s 11103.194us 1 1 100.00
hmac_test_sha512_vectors 20.460s 875.550us 1 1 100.00
hmac_test_hmac256_vectors 7.160s 758.535us 1 1 100.00
hmac_test_hmac384_vectors 5.590s 151.363us 1 1 100.00
hmac_test_hmac512_vectors 8.700s 282.619us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.230s 130.966us 1 1 100.00
hmac_long_msg 75.950s 1888.890us 1 1 100.00
hmac_back_pressure 14.940s 1768.875us 1 1 100.00
hmac_datapath_stress 125.310s 3334.131us 1 1 100.00
hmac_burst_wr 3.180s 728.517us 1 1 100.00
hmac_error 30.490s 18368.376us 1 1 100.00
hmac_wipe_secret 13.500s 988.441us 1 1 100.00
hmac_test_sha256_vectors 8.170s 325.709us 1 1 100.00
hmac_test_sha384_vectors 390.880s 11103.194us 1 1 100.00
hmac_test_sha512_vectors 20.460s 875.550us 1 1 100.00
hmac_test_hmac256_vectors 7.160s 758.535us 1 1 100.00
hmac_test_hmac384_vectors 5.590s 151.363us 1 1 100.00
hmac_test_hmac512_vectors 8.700s 282.619us 1 1 100.00
hmac_stress_all 240.700s 22435.606us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 240.700s 22435.606us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.580s 19.979us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.790s 14.309us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.510s 712.571us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.510s 712.571us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.730s 30.797us 1 1 100.00
hmac_csr_rw 0.650s 71.572us 1 1 100.00
hmac_csr_aliasing 6.920s 3368.315us 1 1 100.00
hmac_same_csr_outstanding 2.130s 274.100us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.730s 30.797us 1 1 100.00
hmac_csr_rw 0.650s 71.572us 1 1 100.00
hmac_csr_aliasing 6.920s 3368.315us 1 1 100.00
hmac_same_csr_outstanding 2.130s 274.100us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.860s 571.558us 1 1 100.00
hmac_tl_intg_err 1.730s 391.125us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.730s 391.125us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.230s 130.966us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.630s 152.955us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 48.950s 4499.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.030s 331.956us 1 1 100.00