Simulation Results: i2c

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.19 %
  • code
  • 81.50 %
  • assert
  • 96.19 %
  • func
  • 80.87 %
  • line
  • 96.41 %
  • branch
  • 92.41 %
  • cond
  • 85.19 %
  • toggle
  • 89.45 %
  • FSM
  • 44.05 %
Validation stages
V1
100.00%
V2
87.80%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 23.620s 12232.675us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 11.510s 1043.020us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.930s 24.158us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.750s 35.637us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.480s 434.819us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.430s 60.800us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.980s 28.646us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.750s 35.637us 1 1 100.00
i2c_csr_aliasing 1.430s 60.800us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.770s 48.394us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 104.930s 38576.160us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 2486.420s 50732.257us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.780s 82.295us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 96.990s 4963.509us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 99.900s 2264.095us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.040s 1169.780us 1 1 100.00
i2c_host_fifo_fmt_empty 3.720s 988.750us 1 1 100.00
i2c_host_fifo_reset_rx 5.170s 128.839us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 136.560s 3417.683us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 9.150s 1627.537us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.120s 41.072us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.960s 1618.648us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 254.660s 22674.953us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.910s 710.418us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 7.880s 1044.551us 1 1 100.00
i2c_target_intr_smoke 3.740s 3318.451us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.560s 211.626us 1 1 100.00
i2c_target_fifo_reset_tx 1.140s 229.645us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 26.750s 65514.077us 1 1 100.00
i2c_target_stress_rd 7.880s 1044.551us 1 1 100.00
i2c_target_intr_stress_wr 18.680s 3990.213us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 6.950s 1634.667us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 5.940s 2384.636us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.490s 2364.916us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 19.830s 10013.603us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.890s 500.955us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.360s 96.919us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 2486.420s 50732.257us 1 1 100.00
i2c_host_perf_precise 1.230s 106.882us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 9.150s 1627.537us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 4.970s 301.099us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.950s 570.587us 1 1 100.00
i2c_target_nack_acqfull_addr 2.270s 1975.809us 1 1 100.00
i2c_target_nack_txstretch 1.300s 766.740us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 4.780s 1648.706us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.930s 6616.557us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.880s 18.453us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.740s 34.053us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.650s 120.159us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.650s 120.159us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.930s 24.158us 1 1 100.00
i2c_csr_rw 0.750s 35.637us 1 1 100.00
i2c_csr_aliasing 1.430s 60.800us 1 1 100.00
i2c_same_csr_outstanding 0.980s 23.265us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.930s 24.158us 1 1 100.00
i2c_csr_rw 0.750s 35.637us 1 1 100.00
i2c_csr_aliasing 1.430s 60.800us 1 1 100.00
i2c_same_csr_outstanding 0.980s 23.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.910s 103.308us 1 1 100.00
i2c_sec_cm 1.110s 178.635us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.910s 103.308us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 13.120s 4635.015us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.030s 21.526us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 5.020s 387.688us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 44369637747660884332772232762520240755698141326594206750594869561935967633873 80
UVM_INFO @ 48394310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 71821033419159169073328207246481270276662781264354264384302687307320417364258 158
UVM_INFO @ 38576159807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 80439348871648234632271311975763272602919601989639448909320842180118240273696 84
UVM_INFO @ 1618647708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*])
i2c_target_unexp_stop 97285465323685072193568566156599408234383127899731041118077741993848294479665 78
UVM_INFO @ 21525876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 81843926789338932831921487338860725538859009502367285287109312659685857972043 79
UVM_INFO @ 10013603057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 91013619876501930886920510736597361011051146671900624032275998079197854213064 95
UVM_INFO @ 4635015447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 33200737071125651905518244740035766229493413057158935687274595507114738354630 85
UVM_INFO @ 387687673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
i2c_host_mode_toggle 114773817159343971275280164651707744243722023243005913479324638646562466039946 87
--> EXP:
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