Simulation Results: lc_ctrl/volatile_unlock_disabled

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.47 %
  • code
  • 84.75 %
  • assert
  • 94.13 %
  • func
  • 92.53 %
  • line
  • 97.17 %
  • branch
  • 94.12 %
  • cond
  • 79.38 %
  • toggle
  • 89.54 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.430s 249.002us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.020s 17.193us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.030s 35.207us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 94.542us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.560s 146.636us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.180s 31.567us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.030s 35.207us 1 1 100.00
lc_ctrl_csr_aliasing 1.560s 146.636us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.160s 124.429us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.920s 296.274us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.060s 13.508us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.680s 42.241us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 10.170s 1125.588us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.110s 598.949us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 10.170s 1125.588us 1 1 100.00
lc_ctrl_prog_failure 1.680s 42.241us 1 1 100.00
lc_ctrl_errors 7.110s 598.949us 1 1 100.00
lc_ctrl_security_escalation 4.290s 411.124us 1 1 100.00
lc_ctrl_jtag_state_failure 20.520s 1613.361us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.000s 2197.188us 1 1 100.00
lc_ctrl_jtag_errors 20.070s 930.673us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.780s 406.425us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.180s 1837.572us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.000s 2197.188us 1 1 100.00
lc_ctrl_jtag_errors 20.070s 930.673us 1 1 100.00
lc_ctrl_jtag_access 10.270s 608.893us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.190s 5448.621us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.330s 82.227us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.570s 56.545us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 27.920s 1737.518us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.970s 1752.801us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.290s 59.759us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.660s 106.126us 1 1 100.00
lc_ctrl_jtag_alert_test 2.220s 118.739us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.890s 2700.110us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.060s 16.083us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 216.790s 22249.146us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.350s 16.125us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.820s 205.962us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.820s 205.962us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 17.193us 1 1 100.00
lc_ctrl_csr_rw 1.030s 35.207us 1 1 100.00
lc_ctrl_csr_aliasing 1.560s 146.636us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.730s 340.390us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 17.193us 1 1 100.00
lc_ctrl_csr_rw 1.030s 35.207us 1 1 100.00
lc_ctrl_csr_aliasing 1.560s 146.636us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.730s 340.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.270s 247.174us 1 1 100.00
lc_ctrl_tl_intg_err 1.770s 291.871us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.770s 291.871us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.920s 296.274us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 10.170s 1125.588us 1 1 100.00
lc_ctrl_sec_cm 6.270s 247.174us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 10.170s 1125.588us 1 1 100.00
lc_ctrl_sec_cm 6.270s 247.174us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.170s 1125.588us 1 1 100.00
lc_ctrl_sec_cm 6.270s 247.174us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.170s 1125.588us 1 1 100.00
lc_ctrl_sec_cm 6.270s 247.174us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 10.170s 1125.588us 1 1 100.00
lc_ctrl_sec_cm 6.270s 247.174us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.170s 1125.588us 1 1 100.00
lc_ctrl_sec_cm 6.270s 247.174us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.170s 1125.588us 1 1 100.00
lc_ctrl_sec_cm 6.270s 247.174us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 10.170s 1125.588us 1 1 100.00
lc_ctrl_sec_cm 6.270s 247.174us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.290s 411.124us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.160s 124.429us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.180s 1837.572us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.580s 3949.505us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.580s 3949.505us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 11.970s 3097.651us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.110s 656.631us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.110s 656.631us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 46.170s 7756.488us 1 1 100.00