Simulation Results: lc_ctrl/volatile_unlock_enabled

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.83 %
  • code
  • 84.24 %
  • assert
  • 94.13 %
  • func
  • 94.13 %
  • line
  • 97.06 %
  • branch
  • 93.62 %
  • cond
  • 79.21 %
  • toggle
  • 86.84 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 4.360s 300.569us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.890s 30.067us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.900s 19.009us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.340s 181.094us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.480s 230.299us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.180s 46.166us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.900s 19.009us 1 1 100.00
lc_ctrl_csr_aliasing 1.480s 230.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.820s 1109.521us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.650s 384.406us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.040s 37.837us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.150s 206.246us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.380s 323.129us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.140s 282.620us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.380s 323.129us 1 1 100.00
lc_ctrl_prog_failure 2.150s 206.246us 1 1 100.00
lc_ctrl_errors 5.140s 282.620us 1 1 100.00
lc_ctrl_security_escalation 6.670s 1875.532us 1 1 100.00
lc_ctrl_jtag_state_failure 22.440s 1778.562us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.690s 104.663us 1 1 100.00
lc_ctrl_jtag_errors 40.260s 2078.951us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.150s 481.616us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.500s 384.807us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.690s 104.663us 1 1 100.00
lc_ctrl_jtag_errors 40.260s 2078.951us 1 1 100.00
lc_ctrl_jtag_access 4.080s 495.825us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 16.480s 3527.726us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.180s 112.107us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.920s 153.872us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.570s 869.017us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.720s 3564.744us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.970s 33.450us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.480s 77.744us 1 1 100.00
lc_ctrl_jtag_alert_test 0.910s 85.887us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.780s 657.924us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.070s 14.700us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 320.360s 24920.340us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.720s 21.158us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.430s 433.710us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.430s 433.710us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.890s 30.067us 1 1 100.00
lc_ctrl_csr_rw 0.900s 19.009us 1 1 100.00
lc_ctrl_csr_aliasing 1.480s 230.299us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.300s 240.948us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.890s 30.067us 1 1 100.00
lc_ctrl_csr_rw 0.900s 19.009us 1 1 100.00
lc_ctrl_csr_aliasing 1.480s 230.299us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.300s 240.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.260s 135.770us 1 1 100.00
lc_ctrl_tl_intg_err 3.980s 192.246us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.980s 192.246us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.650s 384.406us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.380s 323.129us 1 1 100.00
lc_ctrl_sec_cm 5.260s 135.770us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.380s 323.129us 1 1 100.00
lc_ctrl_sec_cm 5.260s 135.770us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.380s 323.129us 1 1 100.00
lc_ctrl_sec_cm 5.260s 135.770us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.380s 323.129us 1 1 100.00
lc_ctrl_sec_cm 5.260s 135.770us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.380s 323.129us 1 1 100.00
lc_ctrl_sec_cm 5.260s 135.770us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.380s 323.129us 1 1 100.00
lc_ctrl_sec_cm 5.260s 135.770us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.380s 323.129us 1 1 100.00
lc_ctrl_sec_cm 5.260s 135.770us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.380s 323.129us 1 1 100.00
lc_ctrl_sec_cm 5.260s 135.770us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.670s 1875.532us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.820s 1109.521us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.500s 384.807us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.650s 361.656us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.650s 361.656us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.820s 1044.841us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.520s 2006.999us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.520s 2006.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 47.440s 4604.489us 1 1 100.00