Simulation Results: otbn

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.97 %
  • code
  • 95.41 %
  • assert
  • 89.88 %
  • func
  • 96.61 %
  • block
  • 99.42 %
  • line
  • 99.59 %
  • branch
  • 92.79 %
  • toggle
  • 91.81 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
85.71%
V2S
92.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 8.000s 65.334us 1 1 100.00
single_binary 1 1 100.00
otbn_single 26.000s 131.068us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 31.142us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 14.767us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 66.519us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 6.000s 21.588us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 43.777us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 14.767us 1 1 100.00
otbn_csr_aliasing 6.000s 21.588us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 46.000s 5557.309us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 16.000s 702.420us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 26.000s 112.839us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 144.000s 543.667us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 55.000s 777.439us 1 1 100.00
stress_all 0 1 0.00
otbn_stress_all 43.319s 0.000us 0 1 0.00
lc_escalation 1 1 100.00
otbn_escalate 6.000s 23.983us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 4.000s 6.578us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 8.000s 109.652us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 8.000s 15.438us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 19.600us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 581.050us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 581.050us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 31.142us 1 1 100.00
otbn_csr_rw 4.000s 14.767us 1 1 100.00
otbn_csr_aliasing 6.000s 21.588us 1 1 100.00
otbn_same_csr_outstanding 4.000s 15.895us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 31.142us 1 1 100.00
otbn_csr_rw 4.000s 14.767us 1 1 100.00
otbn_csr_aliasing 6.000s 21.588us 1 1 100.00
otbn_same_csr_outstanding 4.000s 15.895us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 31.829us 1 1 100.00
otbn_dmem_err 6.000s 29.452us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 6.000s 24.158us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 233.099us 1 1 100.00
otbn_mac_bignum_acc_err 10.000s 52.115us 1 1 100.00
otbn_urnd_err 6.000s 22.379us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 4.000s 61.812us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 21.365us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 7.000s 31.557us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 93.000s 1969.050us 1 1 100.00
otbn_tl_intg_err 10.000s 207.608us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 39.000s 750.823us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 93.000s 1969.050us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 93.000s 1969.050us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 8.000s 65.334us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 6.000s 29.452us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 31.829us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 10.000s 207.608us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 23.983us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 31.829us 1 1 100.00
otbn_dmem_err 6.000s 29.452us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 6.578us 0 1 0.00
otbn_illegal_mem_acc 4.000s 61.812us 1 1 100.00
otbn_sec_cm 93.000s 1969.050us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 93.000s 1969.050us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 26.000s 131.068us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 31.829us 1 1 100.00
otbn_dmem_err 6.000s 29.452us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 6.578us 0 1 0.00
otbn_illegal_mem_acc 4.000s 61.812us 1 1 100.00
otbn_sec_cm 93.000s 1969.050us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 93.000s 1969.050us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 23.983us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 31.829us 1 1 100.00
otbn_dmem_err 6.000s 29.452us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 6.578us 0 1 0.00
otbn_illegal_mem_acc 4.000s 61.812us 1 1 100.00
otbn_sec_cm 93.000s 1969.050us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 93.000s 1969.050us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 26.000s 131.068us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 5.000s 86.781us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 95.331us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 40.000s 109.446us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 40.000s 109.446us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 34.887us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 93.000s 1969.050us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 93.000s 1969.050us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 7.000s 59.767us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 93.000s 1969.050us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 93.000s 1969.050us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 63.378us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 63.378us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 3.000s 70.121us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 26.000s 131.068us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 26.000s 131.068us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 26.000s 131.068us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 55.000s 777.439us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 26.000s 131.068us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 26.000s 131.068us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 9.000s 427.022us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 26.000s 131.068us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 93.000s 1969.050us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 138.000s 8389.830us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 33.192us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
otbn_stress_all 66487780043740899992915481964153161811608392172070199008436523281428447940693 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_zero_state_err_urnd 7578901583347876960964225847294701646675371604361657957769357379018511601709 109
UVM_INFO @ 6578388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_urnd_err 97850249596945265346260063743445984810690622449139166259238254942736818528260 108
UVM_INFO @ 22378896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---