Simulation Results: otp_ctrl

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.56 %
  • code
  • 79.03 %
  • assert
  • 93.99 %
  • func
  • 74.66 %
  • line
  • 88.68 %
  • branch
  • 83.92 %
  • cond
  • 91.77 %
  • toggle
  • 87.38 %
  • FSM
  • 43.40 %
Validation stages
V1
100.00%
V2
85.00%
V2S
66.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.480s 191.706us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.570s 630.550us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.670s 256.573us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.650s 40.085us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.610s 464.716us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.120s 1147.037us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.340s 162.530us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.650s 40.085us 1 1 100.00
otp_ctrl_csr_aliasing 5.120s 1147.037us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.110s 44.621us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.090s 41.756us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.850s 1235.771us 1 1 100.00
init_fail 0 1 0.00
otp_ctrl_init_fail 2.940s 380.590us 0 1 0.00
partition_check 1 2 50.00
otp_ctrl_background_chks 19.200s 2257.261us 1 1 100.00
otp_ctrl_check_fail 3.230s 567.926us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 2.970s 124.529us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 10.270s 5086.091us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 14.930s 982.786us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 11.380s 1685.692us 1 1 100.00
otp_ctrl_parallel_lc_esc 6.220s 624.770us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 14.410s 391.551us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 2.610s 106.694us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 11.060s 2920.309us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 107.490s 7325.704us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.690s 54.101us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.800s 242.574us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.900s 120.245us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.900s 120.245us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.670s 256.573us 1 1 100.00
otp_ctrl_csr_rw 1.650s 40.085us 1 1 100.00
otp_ctrl_csr_aliasing 5.120s 1147.037us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.820s 92.200us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.670s 256.573us 1 1 100.00
otp_ctrl_csr_rw 1.650s 40.085us 1 1 100.00
otp_ctrl_csr_aliasing 5.120s 1147.037us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.820s 92.200us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
otp_ctrl_tl_intg_err 8.200s 2636.249us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 8.200s 2636.249us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.570s 630.550us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.570s 630.550us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.220s 624.770us 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.220s 624.770us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.220s 624.770us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.220s 624.770us 1 1 100.00
otp_ctrl_macro_errs 2.610s 106.694us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.220s 624.770us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.220s 624.770us 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.220s 624.770us 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.220s 624.770us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.220s 624.770us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.220s 624.770us 1 1 100.00
otp_ctrl_macro_errs 2.610s 106.694us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.220s 624.770us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.220s 624.770us 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 2.940s 380.590us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.230s 567.926us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 10.270s 5086.091us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 10.270s 5086.091us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 10.270s 5086.091us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 10.270s 5086.091us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 10.270s 5086.091us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.570s 630.550us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 10.270s 5086.091us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.570s 630.550us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 130.570s 20862.911us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 2.970s 124.529us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.570s 630.550us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.570s 630.550us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 2.610s 106.694us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.560s 6043.037us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
otp_ctrl_stress_all_with_rand_reset 4.070s 962.473us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_init_fail 16352027420169768532849309562706750372896002014853350832330618767072224719532 1709
UVM_INFO @ 380590035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state
otp_ctrl_check_fail 16527930264153995658912450502592702863269484504997033423674081263385889238763 1414
UVM_INFO @ 567926176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:*
otp_ctrl_macro_errs 72028539437786851178496330420882730173791887243092826680577156122295985705725 690
UVM_INFO @ 106693842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---