Simulation Results: pwrmgr

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.87 %
  • code
  • 94.55 %
  • assert
  • 96.34 %
  • func
  • 96.71 %
  • line
  • 98.92 %
  • branch
  • 95.61 %
  • cond
  • 94.20 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.670s 41.295us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.920s 36.906us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.770s 30.295us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.760s 47.766us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.930s 33.436us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.280s 93.379us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.770s 30.295us 1 1 100.00
pwrmgr_csr_aliasing 0.930s 33.436us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.930s 93.061us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.930s 93.061us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.650s 68.473us 1 1 100.00
pwrmgr_lowpower_invalid 0.710s 38.024us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.850s 103.208us 1 1 100.00
pwrmgr_reset_invalid 0.920s 108.829us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.850s 103.208us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.020s 209.839us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.800s 181.548us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.780s 66.326us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.690s 1066.401us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.610s 20.769us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.250s 554.325us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.250s 554.325us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.920s 36.906us 1 1 100.00
pwrmgr_csr_rw 0.770s 30.295us 1 1 100.00
pwrmgr_csr_aliasing 0.930s 33.436us 1 1 100.00
pwrmgr_same_csr_outstanding 0.830s 47.761us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.920s 36.906us 1 1 100.00
pwrmgr_csr_rw 0.770s 30.295us 1 1 100.00
pwrmgr_csr_aliasing 0.930s 33.436us 1 1 100.00
pwrmgr_same_csr_outstanding 0.830s 47.761us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.750s 10.272us 0 1 0.00
pwrmgr_sec_cm 0.710s 39.735us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.710s 39.735us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.710s 39.735us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.750s 10.272us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.810s 1801.531us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 1.020s 209.839us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.810s 289.897us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.680s 34.085us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.710s 39.735us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.710s 39.735us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.710s 39.735us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.620s 48.667us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.720s 39.429us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.070s 320.650us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.770s 30.295us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.770s 30.295us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.830s 103.052us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 6.850s 3331.118us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_tl_intg_err 22962028690815290632020150884969042981781767444393935083017181598336656082744 85
UVM_INFO @ 10271650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 112297672793438259217455671795353937056406385778380052360133431533101345303981 86
UVM_INFO @ 39734717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---