Simulation Results: rom_ctrl/32kb

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.80 %
  • code
  • 96.71 %
  • assert
  • 96.80 %
  • func
  • 96.90 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 98.22 %
  • toggle
  • 99.95 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.410s 138.617us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.070s 175.132us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.290s 384.801us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.890s 126.623us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.230s 216.406us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.380s 431.256us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.290s 384.801us 1 1 100.00
rom_ctrl_csr_aliasing 3.230s 216.406us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.940s 731.135us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.570s 130.287us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.290s 135.712us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 11.390s 1613.271us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.530s 569.969us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.370s 151.128us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.350s 294.190us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.350s 294.190us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.070s 175.132us 1 1 100.00
rom_ctrl_csr_rw 3.290s 384.801us 1 1 100.00
rom_ctrl_csr_aliasing 3.230s 216.406us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.370s 174.740us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.070s 175.132us 1 1 100.00
rom_ctrl_csr_rw 3.290s 384.801us 1 1 100.00
rom_ctrl_csr_aliasing 3.230s 216.406us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.370s 174.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 41.770s 3398.702us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.710s 589.548us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 96.740s 1429.763us 1 1 100.00
rom_ctrl_tl_intg_err 46.780s 490.905us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 96.740s 1429.763us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 96.740s 1429.763us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 41.770s 3398.702us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 41.770s 3398.702us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 41.770s 3398.702us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 41.770s 3398.702us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 41.770s 3398.702us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 96.740s 1429.763us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 96.740s 1429.763us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.410s 138.617us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.410s 138.617us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.410s 138.617us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 46.780s 490.905us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 41.770s 3398.702us 1 1 100.00
rom_ctrl_kmac_err_chk 7.530s 569.969us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 41.770s 3398.702us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 41.770s 3398.702us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 41.770s 3398.702us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.710s 589.548us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 96.740s 1429.763us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 201.570s 2904.286us 1 1 100.00