Simulation Results: rstmgr

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 99.22 %
  • assert
  • 96.65 %
  • func
  • 96.52 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.47 %
  • toggle
  • 99.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.380s 207.874us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.870s 80.605us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.900s 51.694us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.960s 1024.366us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.810s 162.416us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.140s 106.107us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.900s 51.694us 1 1 100.00
rstmgr_csr_aliasing 1.810s 162.416us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.900s 203.655us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.310s 126.539us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.820s 84.453us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.790s 856.075us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.790s 856.075us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.790s 856.075us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.790s 856.075us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 22.100s 7994.420us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.890s 64.580us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.280s 100.074us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.280s 100.074us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.870s 80.605us 1 1 100.00
rstmgr_csr_rw 0.900s 51.694us 1 1 100.00
rstmgr_csr_aliasing 1.810s 162.416us 1 1 100.00
rstmgr_same_csr_outstanding 1.300s 105.167us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.870s 80.605us 1 1 100.00
rstmgr_csr_rw 0.900s 51.694us 1 1 100.00
rstmgr_csr_aliasing 1.810s 162.416us 1 1 100.00
rstmgr_same_csr_outstanding 1.300s 105.167us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 11.050s 8485.464us 1 1 100.00
rstmgr_tl_intg_err 1.640s 415.741us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 11.050s 8485.464us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 11.050s 8485.464us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.640s 415.741us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.970s 156.409us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.630s 2455.512us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.130s 302.239us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 11.050s 8485.464us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.900s 51.694us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.900s 51.694us 1 1 100.00