Simulation Results: rv_timer

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.18 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 94.71 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.710s 139.973us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.580s 18.035us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.650s 14.984us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.900s 425.734us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.750s 115.331us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.850s 178.874us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.650s 14.984us 1 1 100.00
rv_timer_csr_aliasing 0.750s 115.331us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.640s 164.021us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.640s 3158.040us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 118.440s 102054.673us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 118.440s 102054.673us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.880s 5015.293us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.590s 16.047us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.640s 27.455us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.020s 46.365us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.020s 46.365us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.580s 18.035us 1 1 100.00
rv_timer_csr_rw 0.650s 14.984us 1 1 100.00
rv_timer_csr_aliasing 0.750s 115.331us 1 1 100.00
rv_timer_same_csr_outstanding 0.620s 17.420us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.580s 18.035us 1 1 100.00
rv_timer_csr_rw 0.650s 14.984us 1 1 100.00
rv_timer_csr_aliasing 0.750s 115.331us 1 1 100.00
rv_timer_same_csr_outstanding 0.620s 17.420us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.770s 175.846us 1 1 100.00
rv_timer_tl_intg_err 1.220s 607.484us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.220s 607.484us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.580s 26.105us 1 1 100.00
max_value 1 1 100.00
rv_timer_max 0.710s 22.948us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 15.580s 2900.519us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 72685659018916625556656544451452623798489239879768292333025995594551661170974 75
UVM_INFO @ 164021260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---