Simulation Results: spi_device/1r1w

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.64 %
  • code
  • 93.31 %
  • assert
  • 87.66 %
  • func
  • 75.94 %
  • line
  • 99.10 %
  • branch
  • 98.37 %
  • cond
  • 96.16 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 49.710s 6254.905us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.960s 77.348us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.530s 135.096us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 26.060s 3607.508us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.370s 416.875us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.850s 85.021us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.530s 135.096us 1 1 100.00
spi_device_csr_aliasing 5.370s 416.875us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.780s 28.034us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.500s 39.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.760s 61.692us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.780s 1.683us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.830s 5.560us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.290s 34.364us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.290s 34.364us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 13.840s 6338.569us 1 1 100.00
spi_device_tpm_sts_read 1.190s 125.309us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 28.040s 25073.712us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.750s 126.161us 1 1 100.00
spi_device_flash_all 28.770s 18141.645us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 8.310s 3052.166us 1 1 100.00
spi_device_flash_all 28.770s 18141.645us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 8.310s 3052.166us 1 1 100.00
spi_device_flash_all 28.770s 18141.645us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 28.770s 18141.645us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.610s 88.721us 1 1 100.00
spi_device_flash_all 28.770s 18141.645us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.610s 88.721us 1 1 100.00
spi_device_flash_all 28.770s 18141.645us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.610s 88.721us 1 1 100.00
spi_device_flash_all 28.770s 18141.645us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.610s 88.721us 1 1 100.00
spi_device_flash_all 28.770s 18141.645us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.610s 88.721us 1 1 100.00
spi_device_flash_all 28.770s 18141.645us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.280s 304.449us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 4.960s 4545.036us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 4.960s 4545.036us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 4.960s 4545.036us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.240s 92.092us 1 1 100.00
spi_device_read_buffer_direct 8.340s 2142.950us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 4.960s 4545.036us 1 1 100.00
spi_device_flash_all 28.770s 18141.645us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 28.770s 18141.645us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 28.770s 18141.645us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 6.920s 7366.981us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 6.920s 7366.981us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 49.710s 6254.905us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 58.430s 18000.788us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 151.400s 105043.097us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.710s 37.713us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.820s 137.890us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.270s 49.383us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.270s 49.383us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.960s 77.348us 1 1 100.00
spi_device_csr_rw 1.530s 135.096us 1 1 100.00
spi_device_csr_aliasing 5.370s 416.875us 1 1 100.00
spi_device_same_csr_outstanding 2.620s 174.145us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.960s 77.348us 1 1 100.00
spi_device_csr_rw 1.530s 135.096us 1 1 100.00
spi_device_csr_aliasing 5.370s 416.875us 1 1 100.00
spi_device_same_csr_outstanding 2.620s 174.145us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.190s 98.870us 1 1 100.00
spi_device_tl_intg_err 14.730s 1131.244us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 14.730s 1131.244us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 29.380s 8863.470us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 58334637990718838784052770060707772522450025878703512731459914350810919142272 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 943664 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 943664 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[966])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 39131516641842733395460516038004107046864559719461315050297764470929584525958 76
UVM_ERROR @ 3034975 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9dfef3 [100111011111111011110011] vs 0x0 [0])
UVM_ERROR @ 3057975 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x55bb1a [10101011011101100011010] vs 0x0 [0])
UVM_ERROR @ 3137975 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbb7f55 [101110110111111101010101] vs 0x0 [0])
UVM_ERROR @ 3219975 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x38b0a1 [1110001011000010100001] vs 0x0 [0])