Simulation Results: spi_device/2p

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.29 %
  • code
  • 94.12 %
  • assert
  • 94.62 %
  • func
  • 79.12 %
  • line
  • 99.16 %
  • branch
  • 98.49 %
  • cond
  • 96.00 %
  • toggle
  • 87.57 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 79.390s 12490.525us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.220s 22.128us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.530s 521.798us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 16.980s 707.812us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 11.530s 611.988us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.360s 150.061us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.530s 521.798us 1 1 100.00
spi_device_csr_aliasing 11.530s 611.988us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.680s 13.544us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.370s 135.669us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.770s 19.736us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.320s 53.833us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 1.060s 37.353us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.280s 102.170us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.280s 102.170us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.730s 2892.963us 1 1 100.00
spi_device_tpm_sts_read 0.960s 110.806us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 26.720s 6776.983us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.110s 133.524us 1 1 100.00
spi_device_flash_all 53.800s 14302.202us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 30.290s 16894.339us 1 1 100.00
spi_device_flash_all 53.800s 14302.202us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 30.290s 16894.339us 1 1 100.00
spi_device_flash_all 53.800s 14302.202us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 53.800s 14302.202us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 5.580s 4914.560us 1 1 100.00
spi_device_flash_all 53.800s 14302.202us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 5.580s 4914.560us 1 1 100.00
spi_device_flash_all 53.800s 14302.202us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 5.580s 4914.560us 1 1 100.00
spi_device_flash_all 53.800s 14302.202us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 5.580s 4914.560us 1 1 100.00
spi_device_flash_all 53.800s 14302.202us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 5.580s 4914.560us 1 1 100.00
spi_device_flash_all 53.800s 14302.202us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 4.840s 889.978us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 10.910s 5994.821us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 10.910s 5994.821us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 10.910s 5994.821us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.240s 431.554us 1 1 100.00
spi_device_read_buffer_direct 6.210s 1828.909us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 10.910s 5994.821us 1 1 100.00
spi_device_flash_all 53.800s 14302.202us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 53.800s 14302.202us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 53.800s 14302.202us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.880s 154.844us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.880s 154.844us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 79.390s 12490.525us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 84.190s 10649.540us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 346.240s 242801.418us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.790s 11.731us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.060s 23.620us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.050s 25.717us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.050s 25.717us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.220s 22.128us 1 1 100.00
spi_device_csr_rw 1.530s 521.798us 1 1 100.00
spi_device_csr_aliasing 11.530s 611.988us 1 1 100.00
spi_device_same_csr_outstanding 2.360s 215.114us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.220s 22.128us 1 1 100.00
spi_device_csr_rw 1.530s 521.798us 1 1 100.00
spi_device_csr_aliasing 11.530s 611.988us 1 1 100.00
spi_device_same_csr_outstanding 2.360s 215.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.040s 342.706us 1 1 100.00
spi_device_tl_intg_err 13.020s 2721.985us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 13.020s 2721.985us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 167.450s 86706.756us 1 1 100.00