Simulation Results: sram_ctrl/main

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.50 %
  • code
  • 96.18 %
  • assert
  • 96.32 %
  • func
  • 94.00 %
  • block
  • 95.27 %
  • line
  • 95.92 %
  • branch
  • 92.71 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 1892.144us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 54.773us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 21.166us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 123.788us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 55.059us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 366.714us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 21.166us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 55.059us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 164.000s 4026.378us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 108.000s 5163.971us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 16.000s 9098.799us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 93.000s 7291.320us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 131.000s 19781.704us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 30.000s 13144.453us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 14.000s 3490.688us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 30.000s 39873.691us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 345.967us 1 1 100.00
sram_ctrl_partial_access_b2b 148.000s 16963.418us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.000s 694.947us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 2906.420us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 6682.539us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 1793.889us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 360.272us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 211.000s 121018.494us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 20.867us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 68.436us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 68.436us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 54.773us 1 1 100.00
sram_ctrl_csr_rw 2.000s 21.166us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 55.059us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 41.444us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 54.773us 1 1 100.00
sram_ctrl_csr_rw 2.000s 21.166us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 55.059us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 41.444us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 3915.041us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 378.168us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 700.197us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 378.168us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 700.197us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 1793.889us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 1793.889us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 21.166us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 30.000s 39873.691us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 30.000s 39873.691us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 30.000s 39873.691us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 14.000s 3490.688us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 3752.463us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 3915.041us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 3497.124us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1892.144us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1892.144us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 30.000s 39873.691us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 378.168us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 14.000s 3490.688us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 378.168us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 378.168us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 1892.144us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 378.168us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 7.000s 342.661us 1 1 100.00