Simulation Results: sysrst_ctrl

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.06 %
  • code
  • 93.29 %
  • assert
  • 93.01 %
  • func
  • 62.89 %
  • line
  • 96.95 %
  • branch
  • 97.44 %
  • cond
  • 94.49 %
  • toggle
  • 100.00 %
  • FSM
  • 77.56 %
Validation stages
V1
100.00%
V2
94.44%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.660s 2111.100us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.500s 2553.179us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.570s 2233.912us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.800s 2533.079us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 8.940s 4012.460us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.780s 2071.337us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 43.550s 23010.906us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.490s 2958.784us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.890s 2082.866us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.780s 2071.337us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.490s 2958.784us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 54.210s 116965.434us 1 1 100.00
combo_detect_with_pre_cond 0 1 0.00
sysrst_ctrl_combo_detect_with_pre_cond 84.670s 95967.929us 0 1 0.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 22.820s 53745.558us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.620s 4743.954us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.300s 2552.253us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.180s 2330.476us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.970s 3986.686us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.910s 2613.506us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 3.090s 4582.151us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 52.650s 34507.694us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 23.860s 11982.669us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.740s 2042.996us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 3.830s 2012.500us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.540s 2072.750us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.540s 2072.750us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 8.940s 4012.460us 1 1 100.00
sysrst_ctrl_csr_rw 1.780s 2071.337us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.490s 2958.784us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 21.070s 7457.613us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 8.940s 4012.460us 1 1 100.00
sysrst_ctrl_csr_rw 1.780s 2071.337us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.490s 2958.784us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 21.070s 7457.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 10.780s 44142.857us 1 1 100.00
sysrst_ctrl_tl_intg_err 7.870s 43090.766us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 7.870s 43090.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 8.250s 33533.595us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])
sysrst_ctrl_combo_detect_with_pre_cond 35915747612082879336940479421907937832090611871921114265179711917978171755220 717
UVM_ERROR @ 95967928654 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (1 [0x1] vs 9 [0x9])
UVM_INFO @ 95967928654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---