Simulation Results: uart

 
30/04/2026 15:30:31 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.70 %
  • code
  • 94.69 %
  • assert
  • 97.12 %
  • func
  • 50.28 %
  • line
  • 98.86 %
  • branch
  • 96.27 %
  • cond
  • 92.07 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.490s 686.804us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.660s 16.283us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.670s 37.695us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.930s 1682.323us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.060s 62.803us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.790s 34.526us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.670s 37.695us 1 1 100.00
uart_csr_aliasing 1.060s 62.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 87.890s 184541.340us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.490s 686.804us 1 1 100.00
uart_tx_rx 87.890s 184541.340us 1 1 100.00
parity_error 2 2 100.00
uart_intr 10.150s 9862.189us 1 1 100.00
uart_rx_parity_err 5.940s 51811.184us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 87.890s 184541.340us 1 1 100.00
uart_intr 10.150s 9862.189us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 136.600s 365055.135us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 83.600s 73111.317us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 10.760s 37549.644us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 10.150s 9862.189us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 10.150s 9862.189us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 10.150s 9862.189us 1 1 100.00
perf 1 1 100.00
uart_perf 14.800s 1544.663us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 6.160s 6354.535us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 6.160s 6354.535us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 7.550s 12482.417us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 34.020s 35000.720us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.140s 681.618us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 2.220s 1487.346us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 333.380s 103371.846us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 138.360s 56278.358us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.660s 22.477us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.670s 14.953us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.080s 62.384us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.080s 62.384us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.660s 16.283us 1 1 100.00
uart_csr_rw 0.670s 37.695us 1 1 100.00
uart_csr_aliasing 1.060s 62.803us 1 1 100.00
uart_same_csr_outstanding 0.810s 28.600us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.660s 16.283us 1 1 100.00
uart_csr_rw 0.670s 37.695us 1 1 100.00
uart_csr_aliasing 1.060s 62.803us 1 1 100.00
uart_same_csr_outstanding 0.810s 28.600us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.980s 129.018us 1 1 100.00
uart_tl_intg_err 0.860s 86.266us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.860s 86.266us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 24.750s 10505.127us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_noise_filter 43763978549645904065944330297266775872440056479465546581649635500325684660537 77
UVM_ERROR @ 9113607295 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 9113627703 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (194 [0xc2] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 9192545439 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 9192545439 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1