Simulation Results: adc_ctrl

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.78 %
  • code
  • 93.31 %
  • assert
  • 90.92 %
  • func
  • 13.12 %
  • line
  • 98.03 %
  • branch
  • 96.29 %
  • cond
  • 85.98 %
  • toggle
  • 99.76 %
  • FSM
  • 86.49 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 10.260s 5781.657us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.310s 1132.747us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.050s 427.918us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 17.200s 53928.611us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.270s 1079.662us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.770s 564.722us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.050s 427.918us 1 1 100.00
adc_ctrl_csr_aliasing 2.270s 1079.662us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.210s 456.841us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.910s 397.462us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.780s 465.659us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.330s 481.606us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.750s 345.165us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 1.050s 300.986us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.360s 322.485us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.120s 337.182us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 2.120s 3012.060us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 63.280s 38335.526us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 45.960s 119154.207us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 20.520s 39599.409us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.770s 368.341us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.950s 454.416us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.400s 792.472us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.400s 792.472us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.310s 1132.747us 1 1 100.00
adc_ctrl_csr_rw 1.050s 427.918us 1 1 100.00
adc_ctrl_csr_aliasing 2.270s 1079.662us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.940s 4800.680us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.310s 1132.747us 1 1 100.00
adc_ctrl_csr_rw 1.050s 427.918us 1 1 100.00
adc_ctrl_csr_aliasing 2.270s 1079.662us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.940s 4800.680us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 4.990s 8364.250us 1 1 100.00
adc_ctrl_tl_intg_err 5.630s 4726.479us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 5.630s 4726.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.100s 1018.145us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *]
adc_ctrl_filters_polled 70564296649737822788240351838889785284157391271074424741075892999846952396199 389
UVM_INFO @ 456840829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 72204862272030468812610117346661257409822778558803704988727153607518048910255 389
UVM_INFO @ 397462285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 51435645057545910070501404440337303237917332053570919587865377527261392409342 389
UVM_INFO @ 465658860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 77222445304074599273600679673363275101985567362008568212694581265108600724688 389
UVM_INFO @ 481606317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 55565652580234390004554193141099839838617489559509708510974445481508208496454 389
UVM_INFO @ 345164614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 69952430759581977789807956075048775200434180648023610923903712905927511865354 389
UVM_INFO @ 300985699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 79943221462839308335692040135626019441183231291751458103435393179173819831537 389
UVM_INFO @ 337182055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 81415378908511869131583833178965561564117290167946979289533959664559225835449 389
UVM_INFO @ 322484788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 55014527856110482305308047133684297023938397179369913866897877522762477596196 402
UVM_INFO @ 1018145340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 10043511257821128981406277412889427526627443569090426943215889770602910227892 496
UVM_INFO @ 39599408997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---