Simulation Results: aes/masked

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.00 %
  • code
  • 95.11 %
  • assert
  • 98.29 %
  • func
  • 67.59 %
  • block
  • 95.72 %
  • line
  • 97.41 %
  • branch
  • 89.48 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
89.47%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 57.232us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 158.685us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 64.551us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 85.417us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 623.223us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 298.925us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 115.507us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 85.417us 1 1 100.00
aes_csr_aliasing 3.000s 298.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 158.685us 1 1 100.00
aes_config_error 4.000s 990.613us 1 1 100.00
aes_stress 4.000s 133.998us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 158.685us 1 1 100.00
aes_config_error 4.000s 990.613us 1 1 100.00
aes_stress 4.000s 133.998us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 133.998us 1 1 100.00
aes_b2b 9.000s 304.744us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 133.998us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 158.685us 1 1 100.00
aes_config_error 4.000s 990.613us 1 1 100.00
aes_stress 4.000s 133.998us 1 1 100.00
aes_alert_reset 44.000s 10024.358us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 3.000s 74.127us 1 1 100.00
aes_config_error 4.000s 990.613us 1 1 100.00
aes_alert_reset 44.000s 10024.358us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 138.310us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 1087.976us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 6.000s 1127.592us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 44.000s 10024.358us 0 1 0.00
stress 1 1 100.00
aes_stress 4.000s 133.998us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 133.998us 1 1 100.00
aes_sideload 4.000s 198.575us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 380.415us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 21.000s 11225.084us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 144.470us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 81.247us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 69.827us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 69.827us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 64.551us 1 1 100.00
aes_csr_rw 2.000s 85.417us 1 1 100.00
aes_csr_aliasing 3.000s 298.925us 1 1 100.00
aes_same_csr_outstanding 3.000s 149.834us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 64.551us 1 1 100.00
aes_csr_rw 2.000s 85.417us 1 1 100.00
aes_csr_aliasing 3.000s 298.925us 1 1 100.00
aes_same_csr_outstanding 3.000s 149.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 5.000s 111.360us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 8.000s 10151.296us 0 1 0.00
aes_control_fi 2.000s 56.906us 1 1 100.00
aes_cipher_fi 13.000s 10017.252us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 91.359us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 91.359us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 91.359us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 91.359us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 133.586us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 742.308us 1 1 100.00
aes_tl_intg_err 2.000s 87.518us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 87.518us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 44.000s 10024.358us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 91.359us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 91.359us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 158.685us 1 1 100.00
aes_stress 4.000s 133.998us 1 1 100.00
aes_alert_reset 44.000s 10024.358us 0 1 0.00
aes_core_fi 2.000s 127.830us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 144.470us 1 1 100.00
aes_config_error 4.000s 990.613us 1 1 100.00
aes_stress 4.000s 133.998us 1 1 100.00
aes_core_fi 2.000s 127.830us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 91.359us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 68.152us 1 1 100.00
aes_stress 4.000s 133.998us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 133.998us 1 1 100.00
aes_sideload 4.000s 198.575us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 68.152us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 68.152us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 68.152us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 68.152us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 68.152us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 133.998us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 133.998us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 8.000s 10151.296us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 8.000s 10151.296us 0 1 0.00
aes_control_fi 2.000s 56.906us 1 1 100.00
aes_cipher_fi 13.000s 10017.252us 0 1 0.00
aes_ctr_fi 2.000s 88.272us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 8.000s 10151.296us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 8.000s 10151.296us 0 1 0.00
aes_control_fi 2.000s 56.906us 1 1 100.00
aes_cipher_fi 13.000s 10017.252us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 13.000s 10017.252us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 8.000s 10151.296us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 8.000s 10151.296us 0 1 0.00
aes_control_fi 2.000s 56.906us 1 1 100.00
aes_ctr_fi 2.000s 88.272us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 8.000s 10151.296us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 8.000s 10151.296us 0 1 0.00
aes_control_fi 2.000s 56.906us 1 1 100.00
aes_cipher_fi 13.000s 10017.252us 0 1 0.00
aes_ctr_fi 2.000s 88.272us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 44.000s 10024.358us 0 1 0.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 8.000s 10151.296us 0 1 0.00
aes_control_fi 2.000s 56.906us 1 1 100.00
aes_cipher_fi 13.000s 10017.252us 0 1 0.00
aes_ctr_fi 2.000s 88.272us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 8.000s 10151.296us 0 1 0.00
aes_control_fi 2.000s 56.906us 1 1 100.00
aes_cipher_fi 13.000s 10017.252us 0 1 0.00
aes_ctr_fi 2.000s 88.272us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 8.000s 10151.296us 0 1 0.00
aes_control_fi 2.000s 56.906us 1 1 100.00
aes_ctr_fi 2.000s 88.272us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 8.000s 10151.296us 0 1 0.00
aes_ghash_fi 3.000s 82.239us 1 1 100.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 8.000s 10151.296us 0 1 0.00
aes_control_fi 2.000s 56.906us 1 1 100.00
aes_cipher_fi 13.000s 10017.252us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 43.000s 7266.466us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 35180145809787443368112747791184797522173577394044984967862722380538741593062 831
UVM_INFO @ 10024357873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 39957074887771849214099450040613231153139720662772097925740948535270920371531 12221
UVM_INFO @ 11225083749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 30465183084730103234333553325984077753570592631754021771777474984275001656761 468
UVM_INFO @ 10151295930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 50608423710236741101018696792661431706948836984142048622940621365778139405572 141
UVM_INFO @ 10017251767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 105146642671035442485628635711465261006590710408351571935663742883542468635167 1702
UVM_INFO @ 7266466422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---