Simulation Results: aes/unmasked

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.86 %
  • code
  • 91.69 %
  • assert
  • 97.75 %
  • func
  • 62.15 %
  • block
  • 91.93 %
  • line
  • 94.06 %
  • branch
  • 85.46 %
  • toggle
  • 97.90 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
89.47%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 78.303us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 66.812us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 83.221us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 91.019us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 795.733us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 76.958us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 220.597us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 91.019us 1 1 100.00
aes_csr_aliasing 2.000s 76.958us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 66.812us 1 1 100.00
aes_config_error 2.000s 76.351us 1 1 100.00
aes_stress 2.000s 91.690us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 66.812us 1 1 100.00
aes_config_error 2.000s 76.351us 1 1 100.00
aes_stress 2.000s 91.690us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 91.690us 1 1 100.00
aes_b2b 4.000s 101.414us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 91.690us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 66.812us 1 1 100.00
aes_config_error 2.000s 76.351us 1 1 100.00
aes_stress 2.000s 91.690us 1 1 100.00
aes_alert_reset 12.000s 10017.154us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 1.000s 71.609us 1 1 100.00
aes_config_error 2.000s 76.351us 1 1 100.00
aes_alert_reset 12.000s 10017.154us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 74.158us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 218.446us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 825.995us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 12.000s 10017.154us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 91.690us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 91.690us 1 1 100.00
aes_sideload 2.000s 211.873us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 80.611us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 23.000s 10157.912us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 114.204us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 112.559us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 130.169us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 130.169us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 83.221us 1 1 100.00
aes_csr_rw 2.000s 91.019us 1 1 100.00
aes_csr_aliasing 2.000s 76.958us 1 1 100.00
aes_same_csr_outstanding 2.000s 131.622us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 83.221us 1 1 100.00
aes_csr_rw 2.000s 91.019us 1 1 100.00
aes_csr_aliasing 2.000s 76.958us 1 1 100.00
aes_same_csr_outstanding 2.000s 131.622us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 439.079us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 31.000s 10064.979us 0 1 0.00
aes_control_fi 1.000s 55.503us 1 1 100.00
aes_cipher_fi 1.000s 50.634us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 132.720us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 132.720us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 132.720us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 132.720us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 203.958us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 486.144us 1 1 100.00
aes_tl_intg_err 4.000s 1333.860us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 4.000s 1333.860us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 12.000s 10017.154us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 132.720us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 132.720us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 66.812us 1 1 100.00
aes_stress 2.000s 91.690us 1 1 100.00
aes_alert_reset 12.000s 10017.154us 0 1 0.00
aes_core_fi 2.000s 85.600us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 114.204us 1 1 100.00
aes_config_error 2.000s 76.351us 1 1 100.00
aes_stress 2.000s 91.690us 1 1 100.00
aes_core_fi 2.000s 85.600us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 132.720us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 63.973us 1 1 100.00
aes_stress 2.000s 91.690us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 91.690us 1 1 100.00
aes_sideload 2.000s 211.873us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 63.973us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 63.973us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 63.973us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 63.973us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 63.973us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 91.690us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 91.690us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 31.000s 10064.979us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 31.000s 10064.979us 0 1 0.00
aes_control_fi 1.000s 55.503us 1 1 100.00
aes_cipher_fi 1.000s 50.634us 1 1 100.00
aes_ctr_fi 2.000s 194.966us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 31.000s 10064.979us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 31.000s 10064.979us 0 1 0.00
aes_control_fi 1.000s 55.503us 1 1 100.00
aes_cipher_fi 1.000s 50.634us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 50.634us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 31.000s 10064.979us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 31.000s 10064.979us 0 1 0.00
aes_control_fi 1.000s 55.503us 1 1 100.00
aes_ctr_fi 2.000s 194.966us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 31.000s 10064.979us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 31.000s 10064.979us 0 1 0.00
aes_control_fi 1.000s 55.503us 1 1 100.00
aes_cipher_fi 1.000s 50.634us 1 1 100.00
aes_ctr_fi 2.000s 194.966us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 12.000s 10017.154us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 31.000s 10064.979us 0 1 0.00
aes_control_fi 1.000s 55.503us 1 1 100.00
aes_cipher_fi 1.000s 50.634us 1 1 100.00
aes_ctr_fi 2.000s 194.966us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 31.000s 10064.979us 0 1 0.00
aes_control_fi 1.000s 55.503us 1 1 100.00
aes_cipher_fi 1.000s 50.634us 1 1 100.00
aes_ctr_fi 2.000s 194.966us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 31.000s 10064.979us 0 1 0.00
aes_control_fi 1.000s 55.503us 1 1 100.00
aes_ctr_fi 2.000s 194.966us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 31.000s 10064.979us 0 1 0.00
aes_ghash_fi 2.000s 99.419us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 31.000s 10064.979us 0 1 0.00
aes_control_fi 1.000s 55.503us 1 1 100.00
aes_cipher_fi 1.000s 50.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 11.000s 165.107us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 110040321211657467451343878613318570817642684533253348544583274813149281670162 669
UVM_INFO @ 10017153576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 36253747093801547021767022882285003013182945221086809725965047583079879630108 17201
UVM_INFO @ 10157911705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 31184670436141392405027882755562118883281710890153834305795286159104238732249 3307
UVM_INFO @ 10064979418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 15227973996196905172103171331123567878278900320783629298127198381176972207657 537
UVM_INFO @ 165107086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---