Simulation Results: chip

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.39 %
  • code
  • 84.44 %
  • assert
  • 97.37 %
  • func
  • 41.37 %
  • line
  • 93.90 %
  • branch
  • 92.20 %
  • cond
  • 87.72 %
  • toggle
  • 91.25 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
77.70%
V2S
100.00%
V3
65.38%
unmapped
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 189.530s 2749.510us 1 1 100.00
chip_sw_example_rom 82.870s 2960.581us 1 1 100.00
chip_sw_example_manufacturer 183.740s 3144.600us 1 1 100.00
chip_sw_example_concurrency 178.830s 3175.909us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 296.200s 8277.304us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 326.080s 4400.544us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 3525.770s 42442.030us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4625.000s 36766.815us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 54.260s 1953.588us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4625.000s 36766.815us 1 1 100.00
chip_csr_rw 326.080s 4400.544us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 7.250s 230.325us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 316.430s 4104.314us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 316.430s 4104.314us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 316.430s 4104.314us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 400.910s 4119.087us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 400.910s 4119.087us 1 1 100.00
chip_sw_uart_tx_rx_idx1 383.550s 4221.388us 1 1 100.00
chip_sw_uart_tx_rx_idx2 374.900s 4896.602us 1 1 100.00
chip_sw_uart_tx_rx_idx3 358.120s 4471.452us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 298.090s 3796.436us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1011.790s 8911.766us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1037.160s 12706.946us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 166.600s 4861.711us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 166.600s 4861.711us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 0 1 0.00
chip_sw_sleep_pin_mio_dio_val 165.290s 3086.192us 0 1 0.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 267.900s 6087.636us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 206.140s 3594.895us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 112.270s 2964.492us 1 1 100.00
chip_tap_straps_testunlock0 326.940s 6925.619us 1 1 100.00
chip_tap_straps_rma 96.180s 2995.521us 1 1 100.00
chip_tap_straps_prod 90.370s 2329.085us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 163.810s 2720.131us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 852.500s 10156.767us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 345.160s 6217.163us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 345.160s 6217.163us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 652.430s 8743.058us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 938.520s 10810.492us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 400.840s 4490.368us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 637.230s 6296.254us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3595.680s 19212.810us 1 1 100.00
chip_sw_aes_enc_jitter_en 147.600s 2476.258us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 786.280s 6986.334us 1 1 100.00
chip_sw_hmac_enc_jitter_en 143.700s 3598.222us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1039.470s 9263.215us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 212.920s 3410.679us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 330.210s 4014.142us 1 1 100.00
chip_sw_clkmgr_jitter 158.450s 2566.730us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 191.330s 3632.064us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 513.610s 7958.604us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 195.730s 4770.841us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 128.540s 3292.407us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 195.730s 4770.841us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 158.250s 3288.710us 1 1 100.00
chip_sw_aes_smoketest 185.270s 2862.214us 1 1 100.00
chip_sw_aon_timer_smoketest 201.720s 2736.435us 1 1 100.00
chip_sw_clkmgr_smoketest 153.230s 2949.032us 1 1 100.00
chip_sw_csrng_smoketest 179.200s 3153.217us 1 1 100.00
chip_sw_entropy_src_smoketest 692.600s 6024.188us 1 1 100.00
chip_sw_gpio_smoketest 180.040s 3097.094us 1 1 100.00
chip_sw_hmac_smoketest 186.300s 2916.276us 1 1 100.00
chip_sw_kmac_smoketest 189.410s 3511.368us 1 1 100.00
chip_sw_otbn_smoketest 954.330s 8362.592us 1 1 100.00
chip_sw_pwrmgr_smoketest 242.690s 5709.870us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 230.980s 5244.855us 1 1 100.00
chip_sw_rv_plic_smoketest 140.820s 2761.170us 1 1 100.00
chip_sw_rv_timer_smoketest 146.450s 2863.820us 1 1 100.00
chip_sw_rstmgr_smoketest 141.240s 2894.902us 1 1 100.00
chip_sw_sram_ctrl_smoketest 167.490s 2791.476us 1 1 100.00
chip_sw_uart_smoketest 141.430s 2800.465us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 171.460s 2431.734us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 325.190s 5108.934us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8480.990s 64189.814us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3020.810s 15346.338us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 52.537s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 177.060s 2613.945us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 154.220s 3113.965us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7507.960s 55016.663us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7492.530s 58395.276us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 73.340s 2725.734us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 73.340s 2725.734us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4625.000s 36766.815us 1 1 100.00
chip_same_csr_outstanding 2750.570s 27602.929us 1 1 100.00
chip_csr_hw_reset 296.200s 8277.304us 1 1 100.00
chip_csr_rw 326.080s 4400.544us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4625.000s 36766.815us 1 1 100.00
chip_same_csr_outstanding 2750.570s 27602.929us 1 1 100.00
chip_csr_hw_reset 296.200s 8277.304us 1 1 100.00
chip_csr_rw 326.080s 4400.544us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 31.350s 581.266us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 6.850s 42.425us 1 1 100.00
xbar_smoke_large_delays 43.670s 6270.589us 1 1 100.00
xbar_smoke_slow_rsp 59.220s 6670.343us 1 1 100.00
xbar_random_zero_delays 32.090s 465.279us 1 1 100.00
xbar_random_large_delays 108.320s 16201.617us 1 1 100.00
xbar_random_slow_rsp 106.840s 11477.560us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 21.990s 648.056us 1 1 100.00
xbar_error_and_unmapped_addr 6.850s 45.886us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 11.860s 208.593us 1 1 100.00
xbar_error_and_unmapped_addr 6.850s 45.886us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 55.900s 2596.705us 1 1 100.00
xbar_access_same_device_slow_rsp 260.230s 30171.367us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 25.420s 490.136us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 64.530s 1166.306us 1 1 100.00
xbar_stress_all_with_error 130.240s 2689.521us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 305.160s 8984.047us 1 1 100.00
xbar_stress_all_with_reset_error 87.650s 431.214us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3020.810s 15346.338us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2480.760s 25345.845us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2928.530s 16229.092us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 67.686s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 58.119s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 57.446s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 29.952s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 26.399s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 70.033s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 33.943s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 11.168s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 34.963s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 9.061s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 132.662s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 71.563s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 62.536s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 77.113s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 40.963s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 16.750s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 18.350s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 17.010s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 18.060s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 21.910s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 15.940s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 18.020s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 16.630s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 18.680s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 16.890s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 16.490s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 18.130s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.980s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 16.580s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 18.780s 10.200us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 71.872s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 63.434s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 63.873s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 63.936s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 91.963s 0.000us 0 1 0.00
rom_e2e_keymgr_init 1 3 33.33
rom_e2e_keymgr_init_rom_ext_meas 3087.760s 15931.890us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 6008.260s 31588.757us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 3026.600s 15650.742us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3074.570s 16413.391us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3251.530s 35101.808us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3251.530s 35101.808us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 181.400s 2885.269us 1 1 100.00
chip_sw_aes_enc_jitter_en 147.600s 2476.258us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 154.870s 2599.974us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 167.480s 3012.448us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1659.170s 12089.840us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 187.430s 2556.547us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 363.880s 6212.992us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 387.800s 5178.525us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 522.190s 5862.865us 1 1 100.00
chip_plic_all_irqs_10 259.670s 3400.050us 1 1 100.00
chip_plic_all_irqs_20 382.100s 4486.794us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 155.250s 3039.959us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 968.250s 11799.632us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 331.340s 5511.987us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 141.650s 3209.023us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.152s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 971.370s 7346.299us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1129.490s 8791.357us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 855.690s 7986.194us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8071.460s 254971.205us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 237.110s 3918.575us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 242.690s 5709.870us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 237.110s 3918.575us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 624.600s 9010.116us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 624.600s 9010.116us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 281.110s 6757.589us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 353.370s 4781.815us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 565.960s 6087.608us 1 1 100.00
chip_sw_aes_idle 167.480s 3012.448us 1 1 100.00
chip_sw_hmac_enc_idle 168.100s 2968.386us 1 1 100.00
chip_sw_kmac_idle 174.210s 3162.811us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 240.820s 4407.476us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 274.110s 3796.599us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 308.330s 5805.404us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 247.870s 4701.041us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 806.500s 10579.582us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 406.470s 4041.121us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 408.750s 4954.519us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 394.170s 4033.821us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 423.250s 4963.127us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 398.600s 4000.571us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 379.430s 5482.014us 1 1 100.00
chip_sw_ast_clk_outputs 652.430s 8743.058us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 281.520s 6537.691us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 394.170s 4033.821us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 423.250s 4963.127us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 400.840s 4490.368us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 637.230s 6296.254us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3595.680s 19212.810us 1 1 100.00
chip_sw_aes_enc_jitter_en 147.600s 2476.258us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 786.280s 6986.334us 1 1 100.00
chip_sw_hmac_enc_jitter_en 143.700s 3598.222us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1039.470s 9263.215us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 212.920s 3410.679us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 330.210s 4014.142us 1 1 100.00
chip_sw_clkmgr_jitter 158.450s 2566.730us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 151.240s 3293.828us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 399.240s 5168.861us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 701.200s 7670.303us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3995.410s 24784.752us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 191.740s 3708.633us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 161.750s 3356.395us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 935.680s 9608.575us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 168.090s 3636.063us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 355.210s 5170.325us 1 1 100.00
chip_sw_flash_init_reduced_freq 1210.270s 22364.380us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 11089.720s 129007.100us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 652.430s 8743.058us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 336.290s 4818.070us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 322.370s 3794.695us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 387.800s 5178.525us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 971.370s 7346.299us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2046.210s 24116.732us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 154.980s 2968.172us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 478.510s 8126.596us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 171.940s 3367.251us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 5544.360s 29557.308us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 164.470s 3691.438us 1 1 100.00
chip_sw_edn_entropy_reqs 541.070s 6333.404us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 164.470s 3691.438us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2046.210s 24116.732us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 132.650s 2474.998us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1039.130s 23302.720us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 546.030s 5395.694us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 637.230s 6296.254us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 351.820s 4003.201us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 400.840s 4490.368us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3451.020s 43425.067us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1039.130s 23302.720us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 215.070s 3954.978us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 655.680s 6839.758us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 178.570s 2980.777us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3451.020s 43425.067us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 178.570s 2980.777us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 178.570s 2980.777us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 178.570s 2980.777us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 178.570s 2980.777us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 387.800s 5178.525us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 93.090s 3404.595us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 621.720s 5959.555us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 481.970s 6151.105us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 481.970s 6151.105us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 161.870s 2977.092us 1 1 100.00
chip_sw_hmac_enc_jitter_en 143.700s 3598.222us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 168.100s 2968.386us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1290.350s 9881.149us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 686.100s 5222.680us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 328.640s 4671.059us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 379.770s 5514.973us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 387.820s 4980.815us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 248.500s 3909.720us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 655.680s 6839.758us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1039.470s 9263.215us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1687.020s 12238.007us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1659.170s 12089.840us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2453.000s 13319.203us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 153.710s 3001.572us 1 1 100.00
chip_sw_kmac_mode_kmac 172.860s 2917.106us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 212.920s 3410.679us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 655.680s 6839.758us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 330.820s 6085.448us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 116.660s 2696.584us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1673.420s 11377.498us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 174.210s 3162.811us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 363.880s 6212.992us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 112.270s 2964.492us 1 1 100.00
chip_tap_straps_rma 96.180s 2995.521us 1 1 100.00
chip_tap_straps_prod 90.370s 2329.085us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 150.880s 2986.877us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 330.820s 6085.448us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 330.820s 6085.448us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 330.820s 6085.448us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1586.940s 12795.187us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 178.570s 2980.777us 0 1 0.00
chip_sw_flash_rma_unlocked 3451.020s 43425.067us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 215.530s 3720.192us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 431.130s 7103.304us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 562.650s 7292.489us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 549.730s 6983.681us 0 1 0.00
chip_sw_lc_ctrl_transition 330.820s 6085.448us 1 1 100.00
chip_sw_keymgr_key_derivation 655.680s 6839.758us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 370.060s 8583.399us 1 1 100.00
chip_sw_sram_ctrl_execution_main 359.230s 6617.041us 1 1 100.00
chip_prim_tl_access 93.090s 3404.595us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 281.520s 6537.691us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 406.470s 4041.121us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 408.750s 4954.519us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 394.170s 4033.821us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 423.250s 4963.127us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 398.600s 4000.571us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 379.430s 5482.014us 1 1 100.00
chip_tap_straps_dev 112.270s 2964.492us 1 1 100.00
chip_tap_straps_rma 96.180s 2995.521us 1 1 100.00
chip_tap_straps_prod 90.370s 2329.085us 1 1 100.00
chip_rv_dm_lc_disabled 301.930s 11173.327us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 137.430s 3154.063us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 111.100s 3868.505us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 77.990s 2713.011us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 113.730s 4051.974us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1559.280s 26740.234us 1 1 100.00
chip_rv_dm_lc_disabled 301.930s 11173.327us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 559.890s 9318.951us 0 1 0.00
chip_sw_lc_walkthrough_prod 609.900s 8858.357us 0 1 0.00
chip_sw_lc_walkthrough_prodend 609.770s 8597.444us 1 1 100.00
chip_sw_lc_walkthrough_rma 375.900s 6553.626us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1559.280s 26740.234us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 65.950s 2270.111us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 63.170s 2744.120us 1 1 100.00
rom_volatile_raw_unlock 35.372s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3575.700s 17693.750us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3595.680s 19212.810us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 565.960s 6087.608us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 565.960s 6087.608us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 565.960s 6087.608us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 281.270s 3831.643us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 330.820s 6085.448us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1039.130s 23302.720us 1 1 100.00
chip_sw_otbn_mem_scramble 281.270s 3831.643us 1 1 100.00
chip_sw_keymgr_key_derivation 655.680s 6839.758us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 357.660s 5311.795us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 138.560s 3362.824us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1039.130s 23302.720us 1 1 100.00
chip_sw_otbn_mem_scramble 281.270s 3831.643us 1 1 100.00
chip_sw_keymgr_key_derivation 655.680s 6839.758us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 357.660s 5311.795us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 138.560s 3362.824us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 330.820s 6085.448us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 383.560s 5592.311us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 150.880s 2986.877us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 215.530s 3720.192us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 431.130s 7103.304us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 562.650s 7292.489us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 549.730s 6983.681us 0 1 0.00
chip_sw_lc_ctrl_transition 330.820s 6085.448us 1 1 100.00
chip_prim_tl_access 93.090s 3404.595us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 93.090s 3404.595us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 901.830s 7914.707us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 188.070s 6773.221us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1260.750s 24481.479us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 242.750s 6819.589us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 496.790s 8654.993us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 368.870s 6121.808us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1046.740s 26355.896us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 2 2 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 788.090s 12378.497us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 624.600s 9010.116us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1012.320s 12538.891us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 307.340s 4296.477us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 188.070s 6773.221us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 337.060s 5177.033us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 866.490s 17469.521us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 342.070s 6371.189us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 161.160s 3066.666us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 436.620s 12194.364us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 768.530s 7105.841us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 899.560s 10232.752us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1512.910s 26079.006us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 194.070s 3236.391us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 387.800s 5178.525us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 370.060s 8583.399us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 370.060s 8583.399us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 899.560s 10232.752us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 436.620s 12194.364us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 307.340s 4296.477us 1 1 100.00
chip_sw_pwrmgr_smoketest 242.690s 5709.870us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 255.750s 4037.172us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 345.950s 4980.265us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 212.710s 4231.457us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 968.250s 11799.632us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 133.860s 2335.046us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 387.800s 5178.525us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1129.490s 8791.357us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 434.570s 4779.126us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 481.250s 4157.667us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 165.510s 2775.687us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 138.560s 3362.824us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 345.950s 4980.265us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 345.950s 4980.265us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 720.330s 10653.390us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 873.850s 13779.456us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 255.750s 4037.172us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 174.420s 3649.665us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 273.560s 5959.915us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 96.180s 2995.521us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 301.930s 11173.327us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 522.190s 5862.865us 1 1 100.00
chip_plic_all_irqs_10 259.670s 3400.050us 1 1 100.00
chip_plic_all_irqs_20 382.100s 4486.794us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 192.980s 3453.028us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 142.200s 3436.776us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3020.810s 15346.338us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 435.150s 6088.257us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 216.010s 3423.063us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 193.620s 2999.588us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 146.240s 3052.372us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 357.660s 5311.795us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 330.210s 4014.142us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 493.480s 9823.256us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 430.720s 8328.471us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 359.230s 6617.041us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 387.800s 5178.525us 1 1 100.00
chip_sw_data_integrity_escalation 345.160s 6217.163us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 768.530s 7105.841us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1115.040s 22138.103us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 162.270s 3365.261us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 195.660s 3686.396us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 340.680s 4346.876us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1115.040s 22138.103us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1115.040s 22138.103us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2470.780s 20327.675us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2470.780s 20327.675us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 309.300s 6332.395us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3251.530s 35101.808us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 125.310s 2389.047us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 186.170s 2945.891us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 273.080s 3826.948us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 333.980s 3782.031us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 960.010s 8043.471us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5380.130s 31917.468us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1858.250s 13145.930us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 164.010s 2963.594us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 205.610s 3476.788us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 77.300s 2788.005us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 10221.350s 71720.012us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1136.060s 6787.270us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 164.610s 3898.060us 0 1 0.00
rom_e2e_jtag_debug_dev 153.330s 3868.896us 0 1 0.00
rom_e2e_jtag_debug_rma 166.350s 4298.114us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 55.250s 2308.212us 0 1 0.00
rom_e2e_jtag_inject_dev 70.030s 2398.864us 0 1 0.00
rom_e2e_jtag_inject_rma 69.240s 1978.173us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 151.176s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 242.170s 3708.094us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 317.360s 2741.464us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 514.740s 4148.529us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1487.690s 10214.139us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 225.590s 2497.310us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 592.010s 5031.936us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 76.430s 2508.065us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 166.220s 3710.624us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 335.120s 7165.083us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 284.620s 4905.533us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 899.560s 10232.752us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 164.610s 3898.060us 0 1 0.00
rom_e2e_jtag_debug_dev 153.330s 3868.896us 0 1 0.00
rom_e2e_jtag_debug_rma 166.350s 4298.114us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 319.430s 5859.476us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 387.800s 5178.525us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5738.190s 38583.699us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5738.190s 38583.699us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 148.370s 3783.276us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 400.910s 4119.087us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2942.470s 18659.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 10 70.00
chip_sival_flash_info_access 210.960s 3259.612us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 451.620s 5453.487us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 4.770s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 143.450s 2809.276us 1 1 100.00
chip_sw_otp_ctrl_descrambling 191.580s 2467.839us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 221.270s 4032.529us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 7.687s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 168.780s 3033.637us 1 1 100.00
ate_bootstrap_flash_erase 6720.560s 45183.232us 1 1 100.00
ate_bootstrap_disjoint 9885.800s 84969.667us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*]
chip_sw_sleep_pin_mio_dio_val 18782235396926606272140660481296989579971392726759612437065606832251435228791 451
UVM_INFO @ 3086.192000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch
chip_sw_spi_device_pass_through_collision 93711997051654452807134231541516624885585997350701719143065301355997710827055 322
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 90673952216755719061035057206956995338470718221581445220709860123941581668010 309
UVM_INFO @ 2980.776714 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 20647021574617076923206184502549524428315985220528461702402061116496298695064 342
UVM_INFO @ 6983.681396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 64681834662285710112911735616225119577624071768152293927928787105484955946530 316
UVM_ERROR @ 3710.623992 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3710.623992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 78711642184393566092582020506457674136216888890157378289354376157337549169139 312
UVM_ERROR @ 2968.171682 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2968.171682 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 46063218845587855205846454529255880973772876678687190857411668572234024739950 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 23365755525120953314344082663095989911121565209744871342910374192769776735805 369
UVM_INFO @ 9318.950888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 106967318002512711824240405066115672009171605077914970000553932886229002923512 369
UVM_INFO @ 8858.357352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 7736961793180110525677596413456348693002999868658703808826137115677334028367 341
UVM_INFO @ 6553.625685 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'
chip_sw_pwrmgr_full_aon_reset 83124367851253655286419542256959468095554071345196807546880739748066449374973 314
UVM_ERROR @ 6773.221308 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6773.221308 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 27730634144421420133063835638587815965341889619964148872681237659158282014893 344
UVM_ERROR @ 12194.364000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 12194.364000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'
chip_sw_pwrmgr_sleep_power_glitch_reset 7032727611957481850524019334849085716470958995182482469926887957084709337014 313
UVM_ERROR @ 3066.666032 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3066.666032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 65768790321359666416363305880756286584012926550853239020863274015119410814371 370
UVM_ERROR @ 17469.521356 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 17469.521356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 110104111865334995017351859146735275485342899596147901438673716752408244706574 332
UVM_INFO @ 35101.808402 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:367)] CHECK-fail: Expect alert *!
chip_sw_alert_test 105012836299737063057500902777857873622825854062455345079400869545652361959221 307
UVM_INFO @ 2556.547496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 55374370676272944940081101192606462485782137261039863230612861632739719566571 308
UVM_INFO @ 3209.022800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 55416916332451744366232581067236467510053182990275257640585933073814843923348 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 86908640888678911819419403649414695359900631920572999715499693205285838639345 217
TL item was: req: (cip_tl_seq_item@32255) { a_addr: 'h105d4 a_data: 'h42cfc9f5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h1a2cf d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2725.733658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 72251830272699725844013544998055432178834151693178587689039330976974793297927 224
TL item was: req: (cip_tl_seq_item@31515) { a_addr: 'h105b8 a_data: 'hc074ca1f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h10 a_opcode: 'h4 a_user: 'h18aab d_param: 'h0 d_source: 'h10 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1953.587825 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 75192954856740885073331374440721608350294461851785212026472670144149068953991 343
UVM_INFO @ 3708.093633 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()
chip_sw_pwrmgr_lowpower_cancel 11151621512391420762519643351440265036530505669452430839896878666560297197943 317
UVM_INFO @ 4032.529286 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
chip_sw_pwrmgr_sleep_wake_5_bug 43870560718597805719588205100025979558739959326181732408158221172887011284255 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 112955894987228959356844106813284600124366057527300652570695197997201659620883 None
---- STDERR ----
Another command (pid=364723) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=395090) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 52096612427820182054400783743146263379033346945624893793620018490485082912486 None
Another command (pid=666037) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=671738) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=667660) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 51511850771982368123544298148681030633676952298754224824285337199725180103681 None
Another command (pid=661306) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=676501) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=625058) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 54115513019439033623156477120855923931928313864075774439348365932697337881435 None
Another command (pid=609640) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=622929) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=607573) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 25373018266536789398589066252594977518623472821616942316889673477185736174992 None
Another command (pid=561382) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=443112) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=593352) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 26588338677743221249114708271873628292587923695124571965617925948252439749796 None
Another command (pid=395090) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=446865) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=442232) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 33789858451227905510990172679839344541880846587132957597771161109810358405883 None
Another command (pid=606187) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=576635) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=609926) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 31424343222029588171531974559126529206449633512882863446493109482465583484481 None
Another command (pid=446103) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=545249) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=558446) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 100055069335320395604222129271685317682598691961134644900745456341927903789376 None
Another command (pid=615477) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=561382) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=443112) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 96427311189857165989893885037370938040739881260883435816648311013758917271335 None
---- STDERR ----
Another command (pid=550542) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=549594) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 92956754359584973395530058340572172340588956888536489202720915861124026000615 None
---- STDERR ----
Another command (pid=471122) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 81273611949548834276881506660666702612759181203466305215021501228198182658050 None
Another command (pid=370388) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=549212) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=550542) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 43407015312957838465468464497172567171880768039806379041744257853470368295579 None
---- STDERR ----
Another command (pid=474600) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 56791873550354664920499829560972458871485631476508668362673237005357060050187 None
Another command (pid=574815) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=584869) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=567933) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 63246503360657970948651878922848805381890179761794164839293503979642180304427 None
Another command (pid=615477) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=561382) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=443112) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 97790870800492555958833655987393238047151204857027525415145180721473700364620 None
Another command (pid=364723) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=395090) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=376260) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 45849204311192704260411869722099652678565265866625922248653345349798888296593 None
---- STDERR ----
Another command (pid=456297) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=374604) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 54833738516176683856960485663340732106950395260507966034292945663100810418 None
Another command (pid=456297) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=374604) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=471122) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 55171412006752113189313248585267219641417116120523295505969533947762148528026 None
Another command (pid=374604) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=471122) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=471336) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 28607270385425637604836046451467645395850531934060656559900004993432568976563 None
Another command (pid=574815) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=584869) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=567933) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 89159649567210995266327564355119505129050731041658379586379488041973021995691 None
---- STDERR ----
Another command (pid=364723) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=395090) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 76956272223734213362739961698934291619103496448307709947771636052212295678184 None
Another command (pid=395090) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=416236) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=446865) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 113589972569838929331017958364893294717223250244816085514002219000770646603526 None
Another command (pid=589662) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=584869) is running. Waiting for it to complete on the server (server_pid=249069)...
Another command (pid=567933) is running. Waiting for it to complete on the server (server_pid=249069)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 31964011619624173594659312936346598699865344666383308061097380381006249747556 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 8816242565189831487878263199912804066875630078062914483731267304889254297335 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 23469232691206388730680454123620535504662412320313695929468340454309475596072 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 42813551824248557761476169847894742160163819919173584928046500751757459832831 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 17553876752658525664629114431922576327297317862158597812385446145335826832932 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 79280514556221561527204883453338667638611037678966581958653638940217021099007 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 53259008970003311801509199139676447675846538716106295080021934863857390698882 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 4927625910884320052780037063006796823097059950542829189900593526188679211339 265
UVM_INFO @ 11173.327191 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 98022127687856678181560545214973091593789975555037576698726245075037167688295 312
UVM_INFO @ 2613.944500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 94395670473995640296888785870379424122538409275711509831186532587287103425562 318
UVM_INFO @ 3113.965000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 70116568071200280770238999970541424164362508641157064400439032930421773778708 327
UVM_INFO @ 10810.491561 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 83354336288350800114989879711944924597676155478893849923683451378922926207187 362
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 97870634813692049516952823511861878889665748445744452946429961545357639565064 325
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 27845145347079841826155992769902273197068428945449066468136108042047569597646 366
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 934460254484680221047760485611527863379226921918521635102455567806113060079 328
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_prod 70668530812975222423980575146452009585628121930557753928135114824158097008409 368
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 31775711041560503945745693895208421850676453108261963369657529435284316852312 367
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 93082444054803214787710575567028177938301582425682459514885091962999199424799 364
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 90150088452600013752697155630785824767999196341880383070465411303237623836347 326
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 75204917910520871987165706976763995182440814054767964955867944532125804475776 327
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 25832005052900356768408874129363854721217770595822837338110083199510745445114 325
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 54466184844580894698920399974132888728834606928821862410152420907485603477148 325
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 22618485637583479324378685291321563857586641092611277029620177346765050182130 328
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 71899120680012374964960662805054555239772645584029687988138228844641096123355 327
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 114127968882661240534402620071388908818417238254712736042999646529070807344249 326
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 93825896614775093774699432891232330896810565986455906995995146223448193148821 326
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_meas 40675864121162357504483085752292225912141699691099099018673307812078057005920 319
UVM_INFO @ 15931.890376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_invalid_meas 25520142187869156373644149496953534060665724716826965780734788054801294266925 319
UVM_INFO @ 15650.741520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 11414947197252901873156779498805935871943250555063864157590602170315577896659 327
UVM_ERROR @ 5108.933730 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5108.933730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---