Simulation Results: clkmgr

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.89 %
  • code
  • 98.37 %
  • assert
  • 95.06 %
  • func
  • 85.25 %
  • line
  • 99.18 %
  • branch
  • 98.94 %
  • cond
  • 93.90 %
  • toggle
  • 99.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.890s 91.285us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.760s 24.539us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.750s 43.523us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.990s 899.400us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.140s 114.540us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.960s 75.539us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.750s 43.523us 1 1 100.00
clkmgr_csr_aliasing 1.140s 114.540us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.680s 39.022us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.740s 29.165us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.970s 99.060us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.900s 12.482us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.890s 91.285us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 7.240s 2403.048us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 6.840s 1213.842us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 7.240s 2403.048us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 9.620s 2403.183us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.860s 13.669us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.500s 335.008us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.500s 335.008us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.760s 24.539us 1 1 100.00
clkmgr_csr_rw 0.750s 43.523us 1 1 100.00
clkmgr_csr_aliasing 1.140s 114.540us 1 1 100.00
clkmgr_same_csr_outstanding 1.140s 125.587us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.760s 24.539us 1 1 100.00
clkmgr_csr_rw 0.750s 43.523us 1 1 100.00
clkmgr_csr_aliasing 1.140s 114.540us 1 1 100.00
clkmgr_same_csr_outstanding 1.140s 125.587us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_sec_cm 5.310s 2061.035us 1 1 100.00
clkmgr_tl_intg_err 1.840s 398.965us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.460s 217.141us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.460s 217.141us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.460s 217.141us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.460s 217.141us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.770s 204.644us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.840s 398.965us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 7.240s 2403.048us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 6.840s 1213.842us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.460s 217.141us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.730s 16.969us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.780s 57.188us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.760s 37.559us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.910s 25.462us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.690s 16.722us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.750s 43.523us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 5.310s 2061.035us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.750s 43.523us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.750s 43.523us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 5.310s 2061.035us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.770s 351.118us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 12.150s 2132.447us 1 1 100.00