Simulation Results: csrng

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.22 %
  • code
  • 92.21 %
  • assert
  • 92.58 %
  • func
  • 73.86 %
  • block
  • 96.88 %
  • line
  • 97.58 %
  • branch
  • 92.17 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 72.871us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 3.000s 308.566us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 15.307us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 18.000s 522.792us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 23.472us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 1.000s 18.457us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 15.307us 1 1 100.00
csrng_csr_aliasing 2.000s 23.472us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 187.708us 1 1 100.00
alerts 1 1 100.00
csrng_alert 19.000s 1624.801us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 30.439us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 4.000s 176.421us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 4.000s 176.421us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 879.000s 83175.943us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 38.003us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 42.597us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 3.000s 116.790us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 3.000s 116.790us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 3.000s 308.566us 1 1 100.00
csrng_csr_rw 1.000s 15.307us 1 1 100.00
csrng_csr_aliasing 2.000s 23.472us 1 1 100.00
csrng_same_csr_outstanding 2.000s 76.460us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 3.000s 308.566us 1 1 100.00
csrng_csr_rw 1.000s 15.307us 1 1 100.00
csrng_csr_aliasing 2.000s 23.472us 1 1 100.00
csrng_same_csr_outstanding 2.000s 76.460us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 5.000s 152.845us 1 1 100.00
csrng_tl_intg_err 6.000s 194.537us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 57.362us 1 1 100.00
csrng_csr_rw 1.000s 15.307us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 19.000s 1624.801us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 879.000s 83175.943us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 187.708us 1 1 100.00
csrng_err 2.000s 30.439us 1 1 100.00
csrng_sec_cm 5.000s 152.845us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 187.708us 1 1 100.00
csrng_err 2.000s 30.439us 1 1 100.00
csrng_sec_cm 5.000s 152.845us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 187.708us 1 1 100.00
csrng_err 2.000s 30.439us 1 1 100.00
csrng_sec_cm 5.000s 152.845us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 187.708us 1 1 100.00
csrng_err 2.000s 30.439us 1 1 100.00
csrng_sec_cm 5.000s 152.845us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 187.708us 1 1 100.00
csrng_err 2.000s 30.439us 1 1 100.00
csrng_sec_cm 5.000s 152.845us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 19.000s 1624.801us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 187.708us 1 1 100.00
csrng_err 2.000s 30.439us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 879.000s 83175.943us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 19.000s 1624.801us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 6.000s 194.537us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 187.708us 1 1 100.00
csrng_err 2.000s 30.439us 1 1 100.00
csrng_sec_cm 5.000s 152.845us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 187.708us 1 1 100.00
csrng_err 2.000s 30.439us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 187.708us 1 1 100.00
csrng_err 2.000s 30.439us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 187.708us 1 1 100.00
csrng_err 2.000s 30.439us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 187.708us 1 1 100.00
csrng_err 2.000s 30.439us 1 1 100.00
csrng_sec_cm 5.000s 152.845us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 187.708us 1 1 100.00
csrng_err 2.000s 30.439us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 10801.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly
csrng_cmds 110193878065214917744055172367986317536429373199402976539406075738460956332462 148
UVM_INFO @ 176421161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
csrng_stress_all_with_rand_reset 39306303028566913042542759889859905681406353076022233355501142785621759580732 None