Simulation Results: edn/edn0

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.50 %
  • code
  • 78.52 %
  • assert
  • 95.01 %
  • func
  • 79.96 %
  • line
  • 97.07 %
  • branch
  • 89.68 %
  • cond
  • 84.45 %
  • toggle
  • 73.54 %
  • FSM
  • 47.85 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.790s 42.663us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.830s 18.237us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.810s 14.191us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.640s 136.088us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.250s 20.586us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.010s 73.099us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.810s 14.191us 1 1 100.00
edn_csr_aliasing 1.250s 20.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.210s 40.484us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.210s 40.484us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.210s 40.484us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.010s 23.180us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.060s 142.872us 1 1 100.00
errs 1 1 100.00
edn_err 0.970s 58.045us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 20.387us 1 1 100.00
edn_disable_auto_req_mode 1.000s 34.515us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 0.960s 101.592us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.840s 78.851us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.070s 235.798us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.550s 420.450us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.550s 420.450us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.830s 18.237us 1 1 100.00
edn_csr_rw 0.810s 14.191us 1 1 100.00
edn_csr_aliasing 1.250s 20.586us 1 1 100.00
edn_same_csr_outstanding 0.840s 78.053us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.830s 18.237us 1 1 100.00
edn_csr_rw 0.810s 14.191us 1 1 100.00
edn_csr_aliasing 1.250s 20.586us 1 1 100.00
edn_same_csr_outstanding 0.840s 78.053us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.540s 1005.308us 1 1 100.00
edn_tl_intg_err 1.450s 126.774us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 18.184us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.060s 142.872us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.540s 1005.308us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.540s 1005.308us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.540s 1005.308us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.540s 1005.308us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.060s 142.872us 1 1 100.00
edn_sec_cm 3.540s 1005.308us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.060s 142.872us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.450s 126.774us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 18.880s 10296.563us 1 1 100.00