Simulation Results: edn/edn1

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.24 %
  • code
  • 82.44 %
  • assert
  • 97.14 %
  • func
  • 82.14 %
  • line
  • 97.88 %
  • branch
  • 92.42 %
  • cond
  • 90.31 %
  • toggle
  • 87.29 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.850s 17.327us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.950s 19.713us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.720s 30.400us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.530s 36.828us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.150s 60.723us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.410s 28.998us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.720s 30.400us 1 1 100.00
edn_csr_aliasing 1.150s 60.723us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.090s 37.773us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.090s 37.773us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.090s 37.773us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.870s 34.224us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.040s 62.555us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 27.093us 1 1 100.00
disable 2 2 100.00
edn_disable 0.730s 38.262us 1 1 100.00
edn_disable_auto_req_mode 0.850s 21.912us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.070s 247.541us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.950s 15.636us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.920s 43.101us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.260s 43.366us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.260s 43.366us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.950s 19.713us 1 1 100.00
edn_csr_rw 0.720s 30.400us 1 1 100.00
edn_csr_aliasing 1.150s 60.723us 1 1 100.00
edn_same_csr_outstanding 0.920s 18.556us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.950s 19.713us 1 1 100.00
edn_csr_rw 0.720s 30.400us 1 1 100.00
edn_csr_aliasing 1.150s 60.723us 1 1 100.00
edn_same_csr_outstanding 0.920s 18.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.330s 364.147us 1 1 100.00
edn_tl_intg_err 2.040s 121.556us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.880s 17.013us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.040s 62.555us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.330s 364.147us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.330s 364.147us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.330s 364.147us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.330s 364.147us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.040s 62.555us 1 1 100.00
edn_sec_cm 3.330s 364.147us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.040s 62.555us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.040s 121.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 61.690s 4201.864us 1 1 100.00