Simulation Results: flash_ctrl

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.70 %
  • code
  • 94.21 %
  • assert
  • 96.76 %
  • func
  • 96.13 %
  • line
  • 95.99 %
  • branch
  • 97.19 %
  • cond
  • 93.32 %
  • toggle
  • 97.49 %
  • FSM
  • 87.07 %
Validation stages
V1
100.00%
V2
98.28%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 64.580s 26.511us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 18.080s 30.507us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 15.140s 120.754us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.450s 67.923us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 28.380s 1643.413us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 32.360s 809.299us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 6.640s 203.851us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.450s 67.923us 1 1 100.00
flash_ctrl_csr_aliasing 32.360s 809.299us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.180s 17.387us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.690s 17.957us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 16.750s 45.229us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 17.860s 123.164us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1301.990s 255574.795us 1 1 100.00
flash_ctrl_hw_rma_reset 562.590s 40128.160us 1 1 100.00
flash_ctrl_lcmgr_intg 5.790s 21.060us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1779.260s 251415.970us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 157.960s 1452.637us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 8.970s 38.824us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2544.900s 49894.498us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 37.470s 167.448us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 12.430s 31.561us 1 1 100.00
flash_ctrl_rw_evict_all_en 12.770s 66.149us 1 1 100.00
flash_ctrl_re_evict 17.020s 111.985us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 109.140s 75.401us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 109.140s 75.401us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 90.760s 3730.602us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 11.490s 617.608us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 217.060s 435.040us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 312.380s 15094.810us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 329.580s 2089.979us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1010.840s 669.149us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.710s 23.983us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 123.230s 5573.517us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.160s 34.151us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.550s 51.387us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 294.880s 203.046us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 119.150s 10667.922us 1 1 100.00
flash_ctrl_otp_reset 53.150s 79.447us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1301.990s 255574.795us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 95.720s 533.346us 1 1 100.00
flash_ctrl_intr_wr 52.800s 3113.921us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 116.300s 30230.335us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 109.140s 33407.266us 1 1 100.00
invalid_op 0 1 0.00
flash_ctrl_invalid_op 17.220s 732.189us 0 1 0.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 37.040s 2657.294us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.660s 145.766us 1 1 100.00
flash_ctrl_ro_derr 100.240s 1609.720us 1 1 100.00
flash_ctrl_rw_derr 178.130s 1918.008us 1 1 100.00
flash_ctrl_derr_detect 101.960s 793.181us 1 1 100.00
flash_ctrl_integrity 492.900s 4766.588us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.050s 62.611us 1 1 100.00
flash_ctrl_ro_serr 92.760s 4745.043us 1 1 100.00
flash_ctrl_rw_serr 164.630s 7878.194us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 70.740s 1114.874us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 84.700s 6700.487us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 116.920s 2097.252us 1 1 100.00
flash_ctrl_write_word_sweep 6.780s 150.746us 1 1 100.00
flash_ctrl_read_word_sweep 7.950s 84.757us 1 1 100.00
flash_ctrl_ro 75.740s 1239.396us 1 1 100.00
flash_ctrl_rw 420.470s 4688.280us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 24.030s 1310.072us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 676.830s 231790.911us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 70.210s 10065.745us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.410s 92.777us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 10.800s 16.988us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.290s 38.224us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.290s 38.224us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.140s 120.754us 1 1 100.00
flash_ctrl_csr_rw 8.450s 67.923us 1 1 100.00
flash_ctrl_csr_aliasing 32.360s 809.299us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.270s 776.457us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.140s 120.754us 1 1 100.00
flash_ctrl_csr_rw 8.450s 67.923us 1 1 100.00
flash_ctrl_csr_aliasing 32.360s 809.299us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.270s 776.457us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 30.250s 82.993us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 30.250s 82.993us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 30.250s 82.993us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 30.250s 82.993us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 24.080s 60.677us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1548.300s 10210.803us 1 1 100.00
flash_ctrl_tl_intg_err 188.280s 1802.597us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 188.280s 1802.597us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 188.280s 1802.597us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 22.580s 109.143us 1 1 100.00
flash_ctrl_wr_intg 6.130s 86.312us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 64.580s 26.511us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 53.150s 79.447us 1 1 100.00
flash_ctrl_disable 9.160s 34.151us 1 1 100.00
flash_ctrl_sec_info_access 32.880s 381.483us 1 1 100.00
flash_ctrl_connect 6.550s 51.387us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.640s 22.577us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.450s 67.923us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 30.250s 82.993us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.450s 67.923us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 30.250s 82.993us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.450s 67.923us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 30.250s 82.993us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.160s 34.151us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 22.580s 109.143us 1 1 100.00
flash_ctrl_access_after_disable 5.490s 76.245us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 11.430s 32.415us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.160s 34.151us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 11.490s 617.608us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 420.470s 4688.280us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 164.630s 7878.194us 1 1 100.00
flash_ctrl_rw_derr 178.130s 1918.008us 1 1 100.00
flash_ctrl_integrity 492.900s 4766.588us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1301.990s 255574.795us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1548.300s 10210.803us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1548.300s 10210.803us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1548.300s 10210.803us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1548.300s 10210.803us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.890s 709.262us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 7.130s 75.404us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 7.240s 69.461us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1548.300s 10210.803us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1548.300s 10210.803us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1548.300s 10210.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 24.000s 88.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 289.330s 1788.033us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly
flash_ctrl_invalid_op 41945386803305187182627014290557065846047493484175599865667203127622162330117 1566
UVM_INFO @ 732189.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---