Simulation Results: hmac

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.04 %
  • code
  • 97.37 %
  • assert
  • 96.70 %
  • func
  • 43.05 %
  • line
  • 99.69 %
  • branch
  • 99.50 %
  • cond
  • 96.46 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.240s 2856.574us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.930s 20.703us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.900s 19.829us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.060s 1222.387us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 7.010s 635.812us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.010s 50.719us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.900s 19.829us 1 1 100.00
hmac_csr_aliasing 7.010s 635.812us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 40.930s 958.835us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 2.950s 58.578us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 173.270s 13100.882us 1 1 100.00
hmac_test_sha384_vectors 20.690s 1744.430us 1 1 100.00
hmac_test_sha512_vectors 22.270s 266.369us 1 1 100.00
hmac_test_hmac256_vectors 9.720s 1149.425us 1 1 100.00
hmac_test_hmac384_vectors 8.410s 497.305us 1 1 100.00
hmac_test_hmac512_vectors 7.800s 931.612us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 10.850s 4102.744us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 340.290s 9154.340us 1 1 100.00
error 1 1 100.00
hmac_error 44.510s 16864.100us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 38.540s 4798.153us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.240s 2856.574us 1 1 100.00
hmac_long_msg 40.930s 958.835us 1 1 100.00
hmac_back_pressure 2.950s 58.578us 1 1 100.00
hmac_datapath_stress 340.290s 9154.340us 1 1 100.00
hmac_burst_wr 10.850s 4102.744us 1 1 100.00
hmac_stress_all 46.180s 5370.882us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.240s 2856.574us 1 1 100.00
hmac_long_msg 40.930s 958.835us 1 1 100.00
hmac_back_pressure 2.950s 58.578us 1 1 100.00
hmac_datapath_stress 340.290s 9154.340us 1 1 100.00
hmac_wipe_secret 38.540s 4798.153us 1 1 100.00
hmac_test_sha256_vectors 173.270s 13100.882us 1 1 100.00
hmac_test_sha384_vectors 20.690s 1744.430us 1 1 100.00
hmac_test_sha512_vectors 22.270s 266.369us 1 1 100.00
hmac_test_hmac256_vectors 9.720s 1149.425us 1 1 100.00
hmac_test_hmac384_vectors 8.410s 497.305us 1 1 100.00
hmac_test_hmac512_vectors 7.800s 931.612us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.240s 2856.574us 1 1 100.00
hmac_long_msg 40.930s 958.835us 1 1 100.00
hmac_back_pressure 2.950s 58.578us 1 1 100.00
hmac_datapath_stress 340.290s 9154.340us 1 1 100.00
hmac_burst_wr 10.850s 4102.744us 1 1 100.00
hmac_error 44.510s 16864.100us 1 1 100.00
hmac_wipe_secret 38.540s 4798.153us 1 1 100.00
hmac_test_sha256_vectors 173.270s 13100.882us 1 1 100.00
hmac_test_sha384_vectors 20.690s 1744.430us 1 1 100.00
hmac_test_sha512_vectors 22.270s 266.369us 1 1 100.00
hmac_test_hmac256_vectors 9.720s 1149.425us 1 1 100.00
hmac_test_hmac384_vectors 8.410s 497.305us 1 1 100.00
hmac_test_hmac512_vectors 7.800s 931.612us 1 1 100.00
hmac_stress_all 46.180s 5370.882us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 46.180s 5370.882us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.610s 21.801us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.650s 11.518us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.990s 516.287us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.990s 516.287us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.930s 20.703us 1 1 100.00
hmac_csr_rw 0.900s 19.829us 1 1 100.00
hmac_csr_aliasing 7.010s 635.812us 1 1 100.00
hmac_same_csr_outstanding 1.600s 130.036us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.930s 20.703us 1 1 100.00
hmac_csr_rw 0.900s 19.829us 1 1 100.00
hmac_csr_aliasing 7.010s 635.812us 1 1 100.00
hmac_same_csr_outstanding 1.600s 130.036us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.850s 57.528us 1 1 100.00
hmac_tl_intg_err 3.640s 910.238us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.640s 910.238us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.240s 2856.574us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.640s 97.932us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 29.100s 3801.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.100s 13.556us 1 1 100.00