Simulation Results: i2c

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.44 %
  • code
  • 81.06 %
  • assert
  • 95.77 %
  • func
  • 79.49 %
  • line
  • 96.35 %
  • branch
  • 92.05 %
  • cond
  • 84.40 %
  • toggle
  • 89.66 %
  • FSM
  • 42.86 %
Validation stages
V1
100.00%
V2
85.37%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 63.400s 1951.374us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 7.340s 1435.144us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.890s 43.788us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 1.020s 45.876us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 4.220s 378.475us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.670s 38.621us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.940s 107.674us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 1.020s 45.876us 1 1 100.00
i2c_csr_aliasing 1.670s 38.621us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.220s 726.722us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 3168.060s 107423.613us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 14.680s 477.003us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.760s 15.671us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 146.220s 3786.753us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 40.230s 9357.935us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.090s 75.685us 1 1 100.00
i2c_host_fifo_fmt_empty 15.800s 469.150us 1 1 100.00
i2c_host_fifo_reset_rx 5.610s 271.892us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 42.220s 4735.698us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 8.740s 616.264us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.680s 19.823us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.910s 1646.442us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 19.430s 5257.736us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.510s 2944.347us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 8.060s 2764.986us 1 1 100.00
i2c_target_intr_smoke 3.160s 3480.976us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 0.920s 137.992us 1 1 100.00
i2c_target_fifo_reset_tx 1.530s 692.283us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 498.790s 49750.324us 1 1 100.00
i2c_target_stress_rd 8.060s 2764.986us 1 1 100.00
i2c_target_intr_stress_wr 96.290s 15681.688us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.460s 2316.952us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 12.720s 2721.968us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 4.020s 5871.544us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 21.440s 10014.275us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.460s 586.507us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.990s 329.601us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 14.680s 477.003us 1 1 100.00
i2c_host_perf_precise 712.150s 23231.624us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 8.740s 616.264us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.380s 86.337us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 2.300s 534.748us 1 1 100.00
i2c_target_nack_acqfull_addr 2.080s 1087.240us 1 1 100.00
i2c_target_nack_txstretch 1.270s 518.071us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 11.880s 1643.749us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.500s 805.530us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.810s 144.076us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.760s 18.026us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.120s 49.062us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.120s 49.062us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.890s 43.788us 1 1 100.00
i2c_csr_rw 1.020s 45.876us 1 1 100.00
i2c_csr_aliasing 1.670s 38.621us 1 1 100.00
i2c_same_csr_outstanding 0.990s 22.415us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.890s 43.788us 1 1 100.00
i2c_csr_rw 1.020s 45.876us 1 1 100.00
i2c_csr_aliasing 1.670s 38.621us 1 1 100.00
i2c_same_csr_outstanding 0.990s 22.415us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.780s 471.380us 1 1 100.00
i2c_sec_cm 0.930s 150.178us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.780s 471.380us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 10.800s 5241.689us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.350s 302.488us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 2.970s 190.603us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 72504536417823124978398725231423002905586110810943554053519754853790331764978 104
UVM_INFO @ 726721980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_mode_toggle 9879057262862554060520656822887953277949021392558063553803906184403248594707 81
UVM_INFO @ 19823335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
i2c_host_stress_all 45853448029284655278113811681826925199957103249300684703949126974422662568031 160
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @50119336
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 70384723474075213947288956041008482706730577908527379633649231392016424931559 84
UVM_INFO @ 1646441954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*])
i2c_target_unexp_stop 84790199633004569501964902419724630359353363184974728794777661238757861699399 78
UVM_INFO @ 302487933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 10486048778415339828153666233067390883820081962569618770105184939602638374344 79
UVM_INFO @ 10014275385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 74564689105152874672729815811918880037333292089276411710520152107733357869193 105
UVM_INFO @ 5241688541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 56552901935210235436332256529878646222843142198155399479340482361028939183928 83
UVM_INFO @ 190602681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *
i2c_target_nack_txstretch 13320457756238095641254428164842829278383802725565836760382799496924465804715 78
UVM_INFO @ 518070896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---