Simulation Results: kmac/masked

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.99 %
  • code
  • 89.58 %
  • assert
  • 97.98 %
  • func
  • 94.41 %
  • line
  • 98.54 %
  • branch
  • 95.59 %
  • cond
  • 91.31 %
  • toggle
  • 99.78 %
  • FSM
  • 62.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 59.550s 8173.040us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.060s 98.204us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.040s 76.215us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 14.870s 4011.227us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.600s 240.872us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.760s 148.946us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.040s 76.215us 1 1 100.00
kmac_csr_aliasing 3.600s 240.872us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.780s 34.887us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.270s 121.954us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1381.010s 67500.616us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 352.920s 13408.955us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 27.470s 1244.511us 1 1 100.00
kmac_test_vectors_sha3_256 29.160s 1961.255us 1 1 100.00
kmac_test_vectors_sha3_384 23.830s 6941.088us 1 1 100.00
kmac_test_vectors_sha3_512 16.190s 2567.703us 1 1 100.00
kmac_test_vectors_shake_128 155.590s 8355.553us 1 1 100.00
kmac_test_vectors_shake_256 1673.300s 58394.152us 1 1 100.00
kmac_test_vectors_kmac 2.740s 245.579us 1 1 100.00
kmac_test_vectors_kmac_xof 1.840s 113.787us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 122.850s 7044.887us 1 1 100.00
app 1 1 100.00
kmac_app 46.420s 3400.031us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 238.620s 24432.576us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 230.970s 5555.872us 1 1 100.00
error 1 1 100.00
kmac_error 96.240s 3104.868us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 9.510s 11351.326us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 3.450s 151.792us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 18.450s 3849.435us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 27.720s 4764.947us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 27.430s 2403.585us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 2.010s 44.371us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 392.150s 92792.482us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.910s 19.417us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.930s 51.166us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.470s 93.090us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.470s 93.090us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.060s 98.204us 1 1 100.00
kmac_csr_rw 1.040s 76.215us 1 1 100.00
kmac_csr_aliasing 3.600s 240.872us 1 1 100.00
kmac_same_csr_outstanding 1.790s 253.655us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.060s 98.204us 1 1 100.00
kmac_csr_rw 1.040s 76.215us 1 1 100.00
kmac_csr_aliasing 3.600s 240.872us 1 1 100.00
kmac_same_csr_outstanding 1.790s 253.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.940s 99.967us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.940s 99.967us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.940s 99.967us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.940s 99.967us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.350s 315.840us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 61.910s 4675.499us 1 1 100.00
kmac_tl_intg_err 2.360s 120.568us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.360s 120.568us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 2.010s 44.371us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 59.550s 8173.040us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 122.850s 7044.887us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.940s 99.967us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 61.910s 4675.499us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 61.910s 4675.499us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 61.910s 4675.499us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 59.550s 8173.040us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 2.010s 44.371us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 61.910s 4675.499us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 20.640s 1293.008us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 59.550s 8173.040us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 46.190s 7564.993us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 113613540254218948994561853830321875824288816102395068069506519368478679846410 212
UVM_INFO @ 7564993335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---