Simulation Results: lc_ctrl/volatile_unlock_disabled

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.63 %
  • code
  • 84.52 %
  • assert
  • 94.13 %
  • func
  • 93.24 %
  • line
  • 97.17 %
  • branch
  • 93.97 %
  • cond
  • 79.17 %
  • toggle
  • 88.72 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.230s 66.705us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.210s 34.406us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.860s 61.734us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.200s 24.629us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.580s 23.892us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.380s 30.536us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.860s 61.734us 1 1 100.00
lc_ctrl_csr_aliasing 1.580s 23.892us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.220s 187.016us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 12.740s 1106.753us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.930s 12.942us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.560s 20.795us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.430s 143.609us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.980s 605.903us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.430s 143.609us 1 1 100.00
lc_ctrl_prog_failure 1.560s 20.795us 1 1 100.00
lc_ctrl_errors 5.980s 605.903us 1 1 100.00
lc_ctrl_security_escalation 4.630s 250.779us 1 1 100.00
lc_ctrl_jtag_state_failure 26.440s 15458.286us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.850s 1498.204us 1 1 100.00
lc_ctrl_jtag_errors 26.120s 2719.321us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.130s 130.593us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.680s 837.779us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.850s 1498.204us 1 1 100.00
lc_ctrl_jtag_errors 26.120s 2719.321us 1 1 100.00
lc_ctrl_jtag_access 6.020s 283.907us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.440s 1452.380us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.490s 753.134us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.940s 193.154us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.630s 671.601us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.010s 966.583us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.220s 29.852us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.880s 146.754us 1 1 100.00
lc_ctrl_jtag_alert_test 1.330s 157.812us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.870s 440.764us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.810s 51.481us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 68.420s 25193.762us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.940s 17.106us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.370s 48.216us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.370s 48.216us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.210s 34.406us 1 1 100.00
lc_ctrl_csr_rw 0.860s 61.734us 1 1 100.00
lc_ctrl_csr_aliasing 1.580s 23.892us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.230s 19.247us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.210s 34.406us 1 1 100.00
lc_ctrl_csr_rw 0.860s 61.734us 1 1 100.00
lc_ctrl_csr_aliasing 1.580s 23.892us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.230s 19.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.110s 246.412us 1 1 100.00
lc_ctrl_tl_intg_err 3.050s 215.858us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.050s 215.858us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 12.740s 1106.753us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.430s 143.609us 1 1 100.00
lc_ctrl_sec_cm 6.110s 246.412us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.430s 143.609us 1 1 100.00
lc_ctrl_sec_cm 6.110s 246.412us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.430s 143.609us 1 1 100.00
lc_ctrl_sec_cm 6.110s 246.412us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.430s 143.609us 1 1 100.00
lc_ctrl_sec_cm 6.110s 246.412us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.430s 143.609us 1 1 100.00
lc_ctrl_sec_cm 6.110s 246.412us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.430s 143.609us 1 1 100.00
lc_ctrl_sec_cm 6.110s 246.412us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.430s 143.609us 1 1 100.00
lc_ctrl_sec_cm 6.110s 246.412us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.430s 143.609us 1 1 100.00
lc_ctrl_sec_cm 6.110s 246.412us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.630s 250.779us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.220s 187.016us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.680s 837.779us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.360s 363.382us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.360s 363.382us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.350s 289.584us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.210s 755.730us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.210s 755.730us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 45.600s 4692.783us 1 1 100.00