Simulation Results: lc_ctrl/volatile_unlock_enabled

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.17 %
  • code
  • 84.31 %
  • assert
  • 93.85 %
  • func
  • 92.35 %
  • line
  • 97.06 %
  • branch
  • 93.47 %
  • cond
  • 79.14 %
  • toggle
  • 88.31 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.130s 65.720us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.920s 29.153us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.750s 27.751us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.460s 79.191us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.630s 34.137us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.040s 65.646us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.750s 27.751us 1 1 100.00
lc_ctrl_csr_aliasing 1.630s 34.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.110s 77.162us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.260s 252.810us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.950s 14.144us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.350s 64.825us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.870s 405.972us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.340s 392.780us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.870s 405.972us 1 1 100.00
lc_ctrl_prog_failure 2.350s 64.825us 1 1 100.00
lc_ctrl_errors 5.340s 392.780us 1 1 100.00
lc_ctrl_security_escalation 4.520s 606.050us 1 1 100.00
lc_ctrl_jtag_state_failure 16.410s 5436.963us 1 1 100.00
lc_ctrl_jtag_prog_failure 12.930s 1265.548us 1 1 100.00
lc_ctrl_jtag_errors 19.710s 7769.228us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.640s 130.884us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.940s 1289.282us 1 1 100.00
lc_ctrl_jtag_prog_failure 12.930s 1265.548us 1 1 100.00
lc_ctrl_jtag_errors 19.710s 7769.228us 1 1 100.00
lc_ctrl_jtag_access 1.300s 147.889us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.900s 787.379us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.640s 454.262us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.440s 305.970us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.620s 15757.184us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.190s 257.518us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.920s 49.514us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.880s 270.100us 1 1 100.00
lc_ctrl_jtag_alert_test 1.150s 42.992us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.170s 522.664us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.230s 64.314us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 54.920s 22587.493us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.780s 83.518us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.530s 80.708us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.530s 80.708us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 29.153us 1 1 100.00
lc_ctrl_csr_rw 0.750s 27.751us 1 1 100.00
lc_ctrl_csr_aliasing 1.630s 34.137us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.450s 43.188us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 29.153us 1 1 100.00
lc_ctrl_csr_rw 0.750s 27.751us 1 1 100.00
lc_ctrl_csr_aliasing 1.630s 34.137us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.450s 43.188us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.840s 252.367us 1 1 100.00
lc_ctrl_tl_intg_err 1.580s 410.718us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.580s 410.718us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.260s 252.810us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.870s 405.972us 1 1 100.00
lc_ctrl_sec_cm 5.840s 252.367us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.870s 405.972us 1 1 100.00
lc_ctrl_sec_cm 5.840s 252.367us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.870s 405.972us 1 1 100.00
lc_ctrl_sec_cm 5.840s 252.367us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.870s 405.972us 1 1 100.00
lc_ctrl_sec_cm 5.840s 252.367us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.870s 405.972us 1 1 100.00
lc_ctrl_sec_cm 5.840s 252.367us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.870s 405.972us 1 1 100.00
lc_ctrl_sec_cm 5.840s 252.367us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.870s 405.972us 1 1 100.00
lc_ctrl_sec_cm 5.840s 252.367us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.870s 405.972us 1 1 100.00
lc_ctrl_sec_cm 5.840s 252.367us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.520s 606.050us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.110s 77.162us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.940s 1289.282us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 11.710s 2083.902us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 11.710s 2083.902us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.430s 289.691us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 11.850s 1087.921us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 11.850s 1087.921us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 9.750s 1068.738us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 74991204329013147191466519369026284428052854458431592695161300274695664618655 1737
UVM_INFO @ 1068738424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---