Simulation Results: otbn

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.31 %
  • code
  • 95.58 %
  • assert
  • 89.88 %
  • func
  • 97.46 %
  • block
  • 99.42 %
  • line
  • 99.59 %
  • branch
  • 92.63 %
  • toggle
  • 92.66 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
92.86%
V2S
92.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 8.000s 432.693us 1 1 100.00
single_binary 1 1 100.00
otbn_single 9.000s 31.446us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 28.000s 47.964us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 28.000s 21.218us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 28.000s 595.901us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 28.000s 81.959us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 28.000s 75.245us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 28.000s 21.218us 1 1 100.00
otbn_csr_aliasing 28.000s 81.959us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 110.000s 6479.853us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 49.000s 4195.807us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 23.000s 57.806us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 40.000s 562.642us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 31.000s 402.762us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 152.000s 830.649us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 24.000s 19.561us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 6.000s 20.382us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 22.426us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 29.000s 15.061us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 14.301us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 568.331us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 568.331us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 28.000s 47.964us 1 1 100.00
otbn_csr_rw 28.000s 21.218us 1 1 100.00
otbn_csr_aliasing 28.000s 81.959us 1 1 100.00
otbn_same_csr_outstanding 4.000s 29.442us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 28.000s 47.964us 1 1 100.00
otbn_csr_rw 28.000s 21.218us 1 1 100.00
otbn_csr_aliasing 28.000s 81.959us 1 1 100.00
otbn_same_csr_outstanding 4.000s 29.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 25.000s 52.607us 1 1 100.00
otbn_dmem_err 27.000s 41.690us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 30.000s 133.892us 1 1 100.00
otbn_controller_ispr_rdata_err 28.000s 29.722us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 199.360us 1 1 100.00
otbn_urnd_err 11.000s 23.048us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 24.000s 23.273us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 15.211us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 17.571us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 382.000s 2553.203us 1 1 100.00
otbn_tl_intg_err 9.000s 833.073us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 37.000s 193.518us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 382.000s 2553.203us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 382.000s 2553.203us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 8.000s 432.693us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 27.000s 41.690us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 25.000s 52.607us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 9.000s 833.073us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 24.000s 19.561us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 25.000s 52.607us 1 1 100.00
otbn_dmem_err 27.000s 41.690us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 20.382us 0 1 0.00
otbn_illegal_mem_acc 24.000s 23.273us 1 1 100.00
otbn_sec_cm 382.000s 2553.203us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 382.000s 2553.203us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 9.000s 31.446us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 25.000s 52.607us 1 1 100.00
otbn_dmem_err 27.000s 41.690us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 20.382us 0 1 0.00
otbn_illegal_mem_acc 24.000s 23.273us 1 1 100.00
otbn_sec_cm 382.000s 2553.203us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 382.000s 2553.203us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 24.000s 19.561us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 25.000s 52.607us 1 1 100.00
otbn_dmem_err 27.000s 41.690us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 20.382us 0 1 0.00
otbn_illegal_mem_acc 24.000s 23.273us 1 1 100.00
otbn_sec_cm 382.000s 2553.203us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 382.000s 2553.203us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 9.000s 31.446us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 27.000s 203.896us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 44.995us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 25.000s 235.206us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 25.000s 235.206us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 20.292us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 382.000s 2553.203us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 382.000s 2553.203us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 7.000s 56.984us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 382.000s 2553.203us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 382.000s 2553.203us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 5.000s 26.386us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 5.000s 26.386us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 42.554us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 31.446us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 31.446us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 9.000s 31.446us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 31.000s 402.762us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 9.000s 31.446us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 9.000s 31.446us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 8.000s 24.966us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 9.000s 31.446us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 382.000s 2553.203us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 433.000s 10745.651us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 137.634us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_zero_state_err_urnd 104949700260811471945161455488506162334383383707561137635986211344792907956267 105
UVM_INFO @ 20381765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_urnd_err 45390265238147919886941527163896221210723310567092534497929345145053115883895 112
UVM_INFO @ 23048074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---