Simulation Results: otp_ctrl

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.00 %
  • code
  • 78.32 %
  • assert
  • 94.11 %
  • func
  • 73.57 %
  • line
  • 88.70 %
  • branch
  • 83.36 %
  • cond
  • 89.99 %
  • toggle
  • 86.65 %
  • FSM
  • 42.88 %
Validation stages
V1
100.00%
V2
85.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.480s 203.970us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.610s 217.973us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.110s 164.133us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.480s 45.025us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.460s 1261.604us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.840s 109.393us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.700s 179.119us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.480s 45.025us 1 1 100.00
otp_ctrl_csr_aliasing 2.840s 109.393us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.200s 533.249us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.150s 144.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.430s 810.126us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.210s 102.114us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 10.780s 637.216us 0 1 0.00
otp_ctrl_check_fail 1.600s 60.657us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 6.840s 593.417us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 15.690s 1228.830us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 15.370s 2260.477us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 10.550s 688.342us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.440s 345.537us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 35.640s 3093.459us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 3.070s 181.239us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 27.930s 13296.170us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 75.190s 49031.582us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.630s 481.687us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.620s 79.130us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.320s 286.284us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.320s 286.284us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.110s 164.133us 1 1 100.00
otp_ctrl_csr_rw 1.480s 45.025us 1 1 100.00
otp_ctrl_csr_aliasing 2.840s 109.393us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.830s 1528.484us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.110s 164.133us 1 1 100.00
otp_ctrl_csr_rw 1.480s 45.025us 1 1 100.00
otp_ctrl_csr_aliasing 2.840s 109.393us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.830s 1528.484us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
otp_ctrl_tl_intg_err 13.970s 5031.879us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 13.970s 5031.879us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.610s 217.973us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.610s 217.973us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.440s 345.537us 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.440s 345.537us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.440s 345.537us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.440s 345.537us 1 1 100.00
otp_ctrl_macro_errs 3.070s 181.239us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.440s 345.537us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.440s 345.537us 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.440s 345.537us 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.440s 345.537us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.440s 345.537us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.440s 345.537us 1 1 100.00
otp_ctrl_macro_errs 3.070s 181.239us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.440s 345.537us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.440s 345.537us 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.210s 102.114us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 1.600s 60.657us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 15.690s 1228.830us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 15.690s 1228.830us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 15.690s 1228.830us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 15.690s 1228.830us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 15.690s 1228.830us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.610s 217.973us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 15.690s 1228.830us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.610s 217.973us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.970s 10841.411us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 6.840s 593.417us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.610s 217.973us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.610s 217.973us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 3.070s 181.239us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 8.630s 3080.413us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 67.620s 22824.088us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_background_chks 55036118332431268680360766753797047909344627962025445543416453287520161403390 11232
UVM_INFO @ 637216364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state
otp_ctrl_check_fail 78086890483689953114477744160406776836993492338828439320652864337052575812886 515
UVM_INFO @ 60656614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_macro_errs 88693305644756009609824111873812605650970723253248532661570762116589677405723 2193
UVM_INFO @ 181239287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 79523731954264220962133077154107781654751190809446341176930832673357364087008 9630
UVM_INFO @ 22824087811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---