Simulation Results: pattgen

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 23.142us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 2.000s 18.106us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 43.881us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 4.000s 1092.171us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 14.522us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 185.241us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 43.881us 1 1 100.00
pattgen_csr_aliasing 2.000s 14.522us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 3602.081s 0.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 10.000s 10161.060us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 94.223us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 2.000s 283.293us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 2.000s 68.037us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 12.493us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 226.118us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 226.118us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 18.106us 1 1 100.00
pattgen_csr_rw 1.000s 43.881us 1 1 100.00
pattgen_csr_aliasing 2.000s 14.522us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 23.623us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 18.106us 1 1 100.00
pattgen_csr_rw 1.000s 43.881us 1 1 100.00
pattgen_csr_aliasing 2.000s 14.522us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 23.623us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 2.000s 284.827us 1 1 100.00
pattgen_sec_cm 2.000s 71.327us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 284.827us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 28.000s 3862.630us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 34.000s 10193.009us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes
pattgen_perf 25065824228611884052422913870822495362181079918922167370928572653913336500315 None
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)
pattgen_inactive_level 55839940485690879822394984903523323474898972470532989465450021624263313900938 99
UVM_INFO @ 10193008997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 40394860349908919051950780549636963139557151401776004276894870702704721724514 185
UVM_ERROR @ 1576770636 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1576770636 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 1576831860 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]