Simulation Results: prim_esc

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.48 %
  • code
  • 87.76 %
  • assert
  • 85.19 %
  • line
  • 92.66 %
  • branch
  • 82.22 %
  • cond
  • 85.37 %
  • toggle
  • 100.00 %
  • FSM
  • 78.57 %
Validation stages
V1
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
prim_esc_request_test 1 1 100.00
prim_esc_test 0.580s 4.866us 1 1 100.00
prim_ping_req_interrupted_by_esc_req_test 1 1 100.00
prim_esc_test 0.580s 4.866us 1 1 100.00
prim_esc_tx_integrity_errors_test 1 1 100.00
prim_esc_test 0.580s 4.866us 1 1 100.00
prim_esc_reverse_ping_timeout_test 1 1 100.00
prim_esc_test 0.580s 4.866us 1 1 100.00
prim_esc_receiver_counter_fail_test 1 1 100.00
prim_esc_test 0.580s 4.866us 1 1 100.00
prim_esc_handshake_with_rand_reset_test 1 1 100.00
prim_esc_test 0.580s 4.866us 1 1 100.00