Simulation Results: pwrmgr

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.57 %
  • code
  • 94.49 %
  • assert
  • 96.34 %
  • func
  • 95.88 %
  • line
  • 98.92 %
  • branch
  • 95.61 %
  • cond
  • 93.92 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.640s 26.186us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.750s 54.458us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.860s 17.598us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.500s 151.322us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.890s 346.265us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.810s 102.367us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.860s 17.598us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 346.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.770s 146.777us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.770s 146.777us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.920s 70.661us 1 1 100.00
pwrmgr_lowpower_invalid 0.800s 99.349us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 1.070s 63.214us 1 1 100.00
pwrmgr_reset_invalid 0.990s 127.291us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 1.070s 63.214us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.830s 215.390us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.730s 85.559us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.800s 60.222us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.000s 1403.176us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.710s 19.667us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.880s 37.726us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.880s 37.726us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.750s 54.458us 1 1 100.00
pwrmgr_csr_rw 0.860s 17.598us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 346.265us 1 1 100.00
pwrmgr_same_csr_outstanding 1.050s 25.815us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.750s 54.458us 1 1 100.00
pwrmgr_csr_rw 0.860s 17.598us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 346.265us 1 1 100.00
pwrmgr_same_csr_outstanding 1.050s 25.815us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.780s 12.021us 0 1 0.00
pwrmgr_sec_cm 0.800s 13.124us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.800s 13.124us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.800s 13.124us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.780s 12.021us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.510s 746.825us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.830s 215.390us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.930s 137.202us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.690s 40.847us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.800s 13.124us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.800s 13.124us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.800s 13.124us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.820s 43.686us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.780s 49.283us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.940s 85.078us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.860s 17.598us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.860s 17.598us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.960s 103.621us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 9.500s 4188.263us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_tl_intg_err 4970613059966917204082382624849093381687758381574257988384233643248845658585 82
UVM_INFO @ 12020977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 72915706968187156262579114858256750960825638426167563003097736754680918475882 80
UVM_INFO @ 13123783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---