Simulation Results: rom_ctrl/32kb

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.42 %
  • code
  • 93.27 %
  • assert
  • 96.80 %
  • func
  • 96.18 %
  • line
  • 99.32 %
  • branch
  • 98.91 %
  • cond
  • 95.84 %
  • toggle
  • 98.93 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.070s 136.517us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.280s 1607.037us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.150s 558.602us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.510s 2106.367us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.450s 536.013us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.510s 176.710us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.150s 558.602us 1 1 100.00
rom_ctrl_csr_aliasing 3.450s 536.013us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.730s 996.078us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.130s 174.757us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.900s 230.832us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 11.710s 451.731us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.750s 345.347us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.260s 179.128us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.310s 182.942us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.310s 182.942us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.280s 1607.037us 1 1 100.00
rom_ctrl_csr_rw 4.150s 558.602us 1 1 100.00
rom_ctrl_csr_aliasing 3.450s 536.013us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.490s 294.674us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.280s 1607.037us 1 1 100.00
rom_ctrl_csr_rw 4.150s 558.602us 1 1 100.00
rom_ctrl_csr_aliasing 3.450s 536.013us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.490s 294.674us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 47.360s 26527.351us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.070s 3306.913us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 200.850s 1151.737us 1 1 100.00
rom_ctrl_tl_intg_err 41.030s 615.471us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 200.850s 1151.737us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 200.850s 1151.737us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 47.360s 26527.351us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 47.360s 26527.351us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 47.360s 26527.351us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 47.360s 26527.351us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 47.360s 26527.351us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 200.850s 1151.737us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 200.850s 1151.737us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.070s 136.517us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.070s 136.517us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.070s 136.517us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 41.030s 615.471us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 47.360s 26527.351us 0 1 0.00
rom_ctrl_kmac_err_chk 7.750s 345.347us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 47.360s 26527.351us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 47.360s 26527.351us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 47.360s 26527.351us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.070s 3306.913us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 200.850s 1151.737us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 36.800s 1433.323us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 98219177266128798505354118967285635809646158860293304285492334703641685163909 98
UVM_INFO @ 26527351175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---