Simulation Results: rom_ctrl/64kb

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.21 %
  • code
  • 97.70 %
  • assert
  • 96.80 %
  • func
  • 97.14 %
  • line
  • 99.46 %
  • branch
  • 98.54 %
  • cond
  • 97.18 %
  • toggle
  • 100.00 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.050s 222.491us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.010s 537.868us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.980s 533.443us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 9.380s 1455.631us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.840s 377.466us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.660s 752.248us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.980s 533.443us 1 1 100.00
rom_ctrl_csr_aliasing 5.840s 377.466us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.550s 357.592us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.920s 387.171us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 8.680s 740.358us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 20.320s 647.332us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 11.620s 4763.305us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.890s 1028.480us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.350s 726.489us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.350s 726.489us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.010s 537.868us 1 1 100.00
rom_ctrl_csr_rw 6.980s 533.443us 1 1 100.00
rom_ctrl_csr_aliasing 5.840s 377.466us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.290s 558.730us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.010s 537.868us 1 1 100.00
rom_ctrl_csr_rw 6.980s 533.443us 1 1 100.00
rom_ctrl_csr_aliasing 5.840s 377.466us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.290s 558.730us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.830s 4779.764us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.150s 4493.151us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 229.380s 554.168us 1 1 100.00
rom_ctrl_tl_intg_err 93.690s 1566.628us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 229.380s 554.168us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 229.380s 554.168us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.830s 4779.764us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.830s 4779.764us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.830s 4779.764us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.830s 4779.764us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.830s 4779.764us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 229.380s 554.168us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 229.380s 554.168us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.050s 222.491us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.050s 222.491us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.050s 222.491us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 93.690s 1566.628us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.830s 4779.764us 1 1 100.00
rom_ctrl_kmac_err_chk 11.620s 4763.305us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.830s 4779.764us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.830s 4779.764us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.830s 4779.764us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.150s 4493.151us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 229.380s 554.168us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 217.540s 9503.309us 1 1 100.00