Simulation Results: rstmgr

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.54 %
  • code
  • 99.24 %
  • assert
  • 97.86 %
  • func
  • 98.51 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.12 %
  • toggle
  • 99.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.240s 190.239us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.910s 108.774us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.850s 73.285us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.320s 270.874us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.250s 112.124us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.310s 163.495us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.850s 73.285us 1 1 100.00
rstmgr_csr_aliasing 1.250s 112.124us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.720s 121.906us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.720s 365.708us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.090s 157.699us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.850s 1362.074us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.850s 1362.074us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.850s 1362.074us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.850s 1362.074us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 25.600s 9923.275us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.850s 79.399us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.980s 341.578us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.980s 341.578us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.910s 108.774us 1 1 100.00
rstmgr_csr_rw 0.850s 73.285us 1 1 100.00
rstmgr_csr_aliasing 1.250s 112.124us 1 1 100.00
rstmgr_same_csr_outstanding 1.220s 206.125us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.910s 108.774us 1 1 100.00
rstmgr_csr_rw 0.850s 73.285us 1 1 100.00
rstmgr_csr_aliasing 1.250s 112.124us 1 1 100.00
rstmgr_same_csr_outstanding 1.220s 206.125us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 22.650s 16792.784us 1 1 100.00
rstmgr_tl_intg_err 2.140s 825.957us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 22.650s 16792.784us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 22.650s 16792.784us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.140s 825.957us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.130s 169.618us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.360s 2249.964us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.080s 301.290us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 22.650s 16792.784us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.850s 73.285us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.850s 73.285us 1 1 100.00