Simulation Results: rv_timer

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.47 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 95.59 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.660s 123.655us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.630s 12.910us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.520s 55.853us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.050s 933.792us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.660s 21.175us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.630s 54.214us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.520s 55.853us 1 1 100.00
rv_timer_csr_aliasing 0.660s 21.175us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.690s 201.402us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.930s 2655.024us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 190.070s 260018.177us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 190.070s 260018.177us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 0.600s 31.801us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.540s 21.253us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.550s 18.448us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.260s 363.153us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.260s 363.153us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.630s 12.910us 1 1 100.00
rv_timer_csr_rw 0.520s 55.853us 1 1 100.00
rv_timer_csr_aliasing 0.660s 21.175us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 77.666us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.630s 12.910us 1 1 100.00
rv_timer_csr_rw 0.520s 55.853us 1 1 100.00
rv_timer_csr_aliasing 0.660s 21.175us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 77.666us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.850s 94.578us 1 1 100.00
rv_timer_tl_intg_err 1.160s 1014.237us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.160s 1014.237us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.760s 339.061us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.570s 43.364us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 42.110s 4955.099us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 34589237948623436901670629321839652975138423137511608383946108507783369353930 75
UVM_INFO @ 339060912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 22469734627180153748847647915935018847077510687494950310549781130619278284264 76
UVM_INFO @ 201402118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 39130869222044680635039802991924585451791947963651069822431839458744372992195 76
UVM_INFO @ 43363759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---