Simulation Results: spi_device/2p

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.00 %
  • code
  • 94.14 %
  • assert
  • 94.62 %
  • func
  • 63.24 %
  • line
  • 99.10 %
  • branch
  • 98.32 %
  • cond
  • 96.18 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 28.790s 8738.324us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.980s 14.084us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.560s 70.879us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 10.260s 943.395us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 15.280s 323.759us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.090s 612.785us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.560s 70.879us 1 1 100.00
spi_device_csr_aliasing 15.280s 323.759us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.660s 11.945us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.480s 160.015us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.970s 55.931us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.040s 73.692us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.930s 26.161us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.860s 729.209us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.860s 729.209us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.420s 1340.858us 1 1 100.00
spi_device_tpm_sts_read 0.710s 51.573us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 16.660s 13163.556us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 12.840s 64055.988us 1 1 100.00
spi_device_flash_all 62.250s 31845.937us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.610s 1823.169us 1 1 100.00
spi_device_flash_all 62.250s 31845.937us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.610s 1823.169us 1 1 100.00
spi_device_flash_all 62.250s 31845.937us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 62.250s 31845.937us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 13.090s 1697.578us 1 1 100.00
spi_device_flash_all 62.250s 31845.937us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 13.090s 1697.578us 1 1 100.00
spi_device_flash_all 62.250s 31845.937us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 13.090s 1697.578us 1 1 100.00
spi_device_flash_all 62.250s 31845.937us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 13.090s 1697.578us 1 1 100.00
spi_device_flash_all 62.250s 31845.937us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 13.090s 1697.578us 1 1 100.00
spi_device_flash_all 62.250s 31845.937us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.400s 59.860us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 129.980s 41505.026us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 129.980s 41505.026us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 129.980s 41505.026us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 5.220s 1317.385us 1 1 100.00
spi_device_read_buffer_direct 4.110s 252.069us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 129.980s 41505.026us 1 1 100.00
spi_device_flash_all 62.250s 31845.937us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 62.250s 31845.937us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 62.250s 31845.937us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 5.650s 897.742us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 5.650s 897.742us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 28.790s 8738.324us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 25.970s 3782.230us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 0.940s 35.302us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.750s 20.741us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.050s 62.341us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.740s 209.632us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.740s 209.632us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.980s 14.084us 1 1 100.00
spi_device_csr_rw 2.560s 70.879us 1 1 100.00
spi_device_csr_aliasing 15.280s 323.759us 1 1 100.00
spi_device_same_csr_outstanding 1.520s 250.494us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.980s 14.084us 1 1 100.00
spi_device_csr_rw 2.560s 70.879us 1 1 100.00
spi_device_csr_aliasing 15.280s 323.759us 1 1 100.00
spi_device_same_csr_outstanding 1.520s 250.494us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.220s 94.063us 1 1 100.00
spi_device_tl_intg_err 5.550s 297.387us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.550s 297.387us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 93.030s 139331.234us 1 1 100.00