Simulation Results: spi_host

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.89 %
  • code
  • 94.78 %
  • assert
  • 95.64 %
  • func
  • 88.24 %
  • block
  • 96.74 %
  • line
  • 98.27 %
  • branch
  • 92.85 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 19.000s 1075.266us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 55.337us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 42.022us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 214.699us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 46.755us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 78.737us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 42.022us 1 1 100.00
spi_host_csr_aliasing 1.000s 46.755us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 82.991us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 59.844us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 23.550us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 107.393us 1 1 100.00
spi_host_error_cmd 1.000s 21.128us 1 1 100.00
spi_host_event 15.000s 3053.609us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 110.547us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 110.547us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 110.547us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 108.103us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 40.186us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 110.547us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 110.547us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 19.000s 1075.266us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 19.000s 1075.266us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 3.000s 553.700us 1 1 100.00
spien 1 1 100.00
spi_host_spien 193.000s 14409.213us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 479.000s 222930.623us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 9.000s 2652.273us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 107.393us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 25.640us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 16.164us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 58.984us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 58.984us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 55.337us 1 1 100.00
spi_host_csr_rw 1.000s 42.022us 1 1 100.00
spi_host_csr_aliasing 1.000s 46.755us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 153.010us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 55.337us 1 1 100.00
spi_host_csr_rw 1.000s 42.022us 1 1 100.00
spi_host_csr_aliasing 1.000s 46.755us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 153.010us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 193.912us 1 1 100.00
spi_host_sec_cm 2.000s 43.919us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 193.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 207.000s 32051.437us 1 1 100.00