Simulation Results: sram_ctrl/main

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.92 %
  • code
  • 96.57 %
  • assert
  • 96.19 %
  • func
  • 95.00 %
  • block
  • 95.81 %
  • line
  • 96.51 %
  • branch
  • 93.68 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 672.638us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 32.005us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 50.120us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 53.531us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 52.772us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 361.683us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 50.120us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 52.772us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 213.000s 17945.211us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 91.000s 5405.108us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 18.000s 19325.486us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 166.000s 3965.777us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 148.000s 28224.786us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 52.000s 12661.256us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 43.000s 27786.031us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 20.000s 14712.993us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 703.716us 1 1 100.00
sram_ctrl_partial_access_b2b 361.000s 54000.405us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 9.000s 7401.952us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 2792.932us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 702.411us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 3796.607us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 353.453us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 121.000s 122646.429us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 14.154us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 567.577us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 567.577us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 32.005us 1 1 100.00
sram_ctrl_csr_rw 1.000s 50.120us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 52.772us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 60.355us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 32.005us 1 1 100.00
sram_ctrl_csr_rw 1.000s 50.120us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 52.772us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 60.355us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 26.000s 29401.606us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 742.110us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 596.487us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 742.110us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 596.487us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 3796.607us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 3796.607us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 50.120us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 20.000s 14712.993us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 20.000s 14712.993us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 20.000s 14712.993us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 43.000s 27786.031us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 705.563us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 26.000s 29401.606us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 6.000s 1338.162us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 672.638us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 672.638us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 20.000s 14712.993us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 742.110us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 43.000s 27786.031us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 742.110us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 742.110us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 672.638us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 742.110us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 19.000s 849.266us 1 1 100.00