Simulation Results: sram_ctrl/ret

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.42 %
  • code
  • 82.78 %
  • assert
  • 96.29 %
  • func
  • 95.20 %
  • block
  • 93.05 %
  • line
  • 94.06 %
  • branch
  • 88.11 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 54.097us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 20.822us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.679us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 186.720us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 47.081us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 22.518us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 11.679us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 47.081us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.000s 93.551us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 969.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 3.000s 792.704us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 151.000s 2796.382us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 423.698us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 16.000s 6503.816us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.000s 322.035us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 14.000s 3769.345us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 34.466us 1 1 100.00
sram_ctrl_partial_access_b2b 235.000s 70354.391us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 136.162us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 145.180us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 133.022us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 208.373us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 110.739us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 25.000s 13160.354us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 16.912us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 86.625us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 86.625us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 20.822us 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.679us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 47.081us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 16.201us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 20.822us 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.679us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 47.081us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 16.201us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 519.491us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 3061.192us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 332.247us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 3061.192us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 332.247us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 208.373us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 208.373us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.679us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 14.000s 3769.345us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 14.000s 3769.345us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 14.000s 3769.345us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.000s 322.035us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 148.990us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 519.491us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 183.416us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 54.097us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 54.097us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 14.000s 3769.345us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 3061.192us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.000s 322.035us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 3061.192us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 3061.192us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 54.097us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 3061.192us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 53.000s 7747.063us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 52063721030643724661236305493940140572253987887959824781161607704735856667897 88
UVM_INFO @ 22517668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---