Simulation Results

Simulation Results: sysrst_ctrl

04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
80.93 %

code
91.48 %

assert
90.71 %

func
60.59 %

line
96.45 %

branch
96.81 %

cond
93.65 %

toggle
100.00 %

FSM
70.51 %

Validation stages

V1		100.00%
V2		94.44%
V2S		100.00%
V3		100.00%

9/9 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	sysrst_ctrl_smoke	1.680s	2127.593us	1	1	100.00
input_output_inverted				1	1	100.00
	sysrst_ctrl_in_out_inverted	1.190s	2530.967us	1	1	100.00
combo_detect_ec_rst				1	1	100.00
	sysrst_ctrl_combo_detect_ec_rst	3.090s	2436.362us	1	1	100.00
combo_detect_ec_rst_with_pre_cond				1	1	100.00
	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	5.800s	2542.633us	1	1	100.00
csr_hw_reset				1	1	100.00
	sysrst_ctrl_csr_hw_reset	3.880s	6058.958us	1	1	100.00
csr_rw				1	1	100.00
	sysrst_ctrl_csr_rw	2.380s	2124.617us	1	1	100.00
csr_bit_bash				1	1	100.00
	sysrst_ctrl_csr_bit_bash	74.760s	39075.807us	1	1	100.00
csr_aliasing				1	1	100.00
	sysrst_ctrl_csr_aliasing	2.910s	2566.774us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.540s	2078.639us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	sysrst_ctrl_csr_rw	2.380s	2124.617us	1	1	100.00
	sysrst_ctrl_csr_aliasing	2.910s	2566.774us	1	1	100.00

17/18 passed

94.44 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
combo_detect				1	1	100.00
	sysrst_ctrl_combo_detect	38.720s	83475.627us	1	1	100.00
combo_detect_with_pre_cond				0	1	0.00
	sysrst_ctrl_combo_detect_with_pre_cond	34.650s	63197.214us	0	1	0.00
auto_block_key_outputs				1	1	100.00
	sysrst_ctrl_auto_blk_key_output	87.900s	181270.354us	1	1	100.00
keyboard_input_triggered_interrupt				1	1	100.00
	sysrst_ctrl_edge_detect	3.130s	3621.703us	1	1	100.00
pin_output_keyboard_inversion_control				1	1	100.00
	sysrst_ctrl_pin_override_test	4.660s	2513.358us	1	1	100.00
pin_input_value_accessibility				1	1	100.00
	sysrst_ctrl_pin_access_test	4.820s	2121.629us	1	1	100.00
ec_power_on_reset				1	1	100.00
	sysrst_ctrl_ec_pwr_on_rst	5.550s	2924.665us	1	1	100.00
flash_write_protect_output				1	1	100.00
	sysrst_ctrl_flash_wr_prot_out	2.890s	2621.383us	1	1	100.00
ultra_low_power_test				1	1	100.00
	sysrst_ctrl_ultra_low_pwr	6.710s	9656.309us	1	1	100.00
sysrst_ctrl_feature_disable				1	1	100.00
	sysrst_ctrl_feature_disable	65.170s	34316.080us	1	1	100.00
stress_all				1	1	100.00
	sysrst_ctrl_stress_all	14.590s	7071.786us	1	1	100.00
alert_test				1	1	100.00
	sysrst_ctrl_alert_test	2.690s	2022.095us	1	1	100.00
intr_test				1	1	100.00
	sysrst_ctrl_intr_test	1.650s	2028.724us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	sysrst_ctrl_tl_errors	2.810s	2147.212us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	sysrst_ctrl_tl_errors	2.810s	2147.212us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	sysrst_ctrl_csr_hw_reset	3.880s	6058.958us	1	1	100.00
	sysrst_ctrl_csr_rw	2.380s	2124.617us	1	1	100.00
	sysrst_ctrl_csr_aliasing	2.910s	2566.774us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	22.400s	7709.014us	1	1	100.00
tl_d_partial_access				4	4	100.00
	sysrst_ctrl_csr_hw_reset	3.880s	6058.958us	1	1	100.00
	sysrst_ctrl_csr_rw	2.380s	2124.617us	1	1	100.00
	sysrst_ctrl_csr_aliasing	2.910s	2566.774us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	22.400s	7709.014us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	sysrst_ctrl_sec_cm	23.030s	42132.793us	1	1	100.00
	sysrst_ctrl_tl_intg_err	26.800s	22306.030us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	sysrst_ctrl_tl_intg_err	26.800s	22306.030us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	sysrst_ctrl_stress_all_with_rand_reset	5.430s	5127.362us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-*
	sysrst_ctrl_combo_detect_with_pre_cond	2210787557421056319890077610980661729163270809824206963596269141587085622500	698	UVM_INFO @ 60883846831 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x22 UVM_INFO @ 60883923755 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x29 UVM_INFO @ 61492392595 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1 UVM_INFO @ 61507213533 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 17