Simulation Results: uart

 
04/05/2026 15:30:28 DVSim: v1.33.1 sha: e056f5d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.65 %
  • code
  • 95.14 %
  • assert
  • 97.12 %
  • func
  • 52.68 %
  • line
  • 99.17 %
  • branch
  • 97.20 %
  • cond
  • 92.65 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.650s 970.972us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.850s 12.710us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.730s 13.044us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.120s 507.069us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.930s 132.727us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.740s 18.439us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.730s 13.044us 1 1 100.00
uart_csr_aliasing 0.930s 132.727us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 40.690s 16986.002us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.650s 970.972us 1 1 100.00
uart_tx_rx 40.690s 16986.002us 1 1 100.00
parity_error 2 2 100.00
uart_intr 122.790s 376712.116us 1 1 100.00
uart_rx_parity_err 376.470s 222140.493us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 40.690s 16986.002us 1 1 100.00
uart_intr 122.790s 376712.116us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 82.320s 117376.316us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 11.200s 37326.900us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 55.270s 92341.320us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 122.790s 376712.116us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 122.790s 376712.116us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 122.790s 376712.116us 1 1 100.00
perf 1 1 100.00
uart_perf 273.270s 14944.068us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.720s 4163.093us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.720s 4163.093us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.410s 992.802us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 8.410s 48479.843us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.430s 1052.867us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 4.020s 2540.292us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 157.700s 121657.715us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 389.490s 111510.278us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.770s 17.683us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.630s 44.954us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.640s 66.463us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.640s 66.463us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.850s 12.710us 1 1 100.00
uart_csr_rw 0.730s 13.044us 1 1 100.00
uart_csr_aliasing 0.930s 132.727us 1 1 100.00
uart_same_csr_outstanding 1.040s 203.247us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.850s 12.710us 1 1 100.00
uart_csr_rw 0.730s 13.044us 1 1 100.00
uart_csr_aliasing 0.930s 132.727us 1 1 100.00
uart_same_csr_outstanding 1.040s 203.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.110s 69.892us 1 1 100.00
uart_tl_intg_err 1.380s 89.825us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.380s 89.825us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 28.650s 11078.540us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_noise_filter 29415923463300676023321224432573148972713685108532412216241532895811101120932 75
UVM_ERROR @ 937651873 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 938551873 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 939251873 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 940051873 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty
uart_stress_all_with_rand_reset 68402097643441297291114249529578864115809471687104744012432972604669919389308 125
UVM_INFO @ 8164420089 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/273
UVM_INFO @ 8438820089 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/273
UVM_INFO @ 8671700089 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/273
UVM_INFO @ 9091820089 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/273