Simulation Results: adc_ctrl

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.12 %
  • code
  • 92.64 %
  • assert
  • 91.09 %
  • func
  • 11.64 %
  • line
  • 98.03 %
  • branch
  • 96.29 %
  • cond
  • 86.06 %
  • toggle
  • 99.05 %
  • FSM
  • 83.78 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 9.220s 5758.398us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.950s 1163.973us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.250s 378.762us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 13.740s 52439.099us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.400s 799.074us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.030s 440.545us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.250s 378.762us 1 1 100.00
adc_ctrl_csr_aliasing 2.400s 799.074us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.150s 324.244us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.120s 309.667us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 1.530s 345.417us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.180s 276.669us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.950s 328.117us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.810s 354.394us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.560s 516.305us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.930s 355.984us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 5.790s 3473.602us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 14.180s 36449.922us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 42.840s 98168.071us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 246.230s 133880.273us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.880s 304.763us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.910s 461.312us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 3.370s 693.060us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 3.370s 693.060us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.950s 1163.973us 1 1 100.00
adc_ctrl_csr_rw 1.250s 378.762us 1 1 100.00
adc_ctrl_csr_aliasing 2.400s 799.074us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.560s 4408.229us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.950s 1163.973us 1 1 100.00
adc_ctrl_csr_rw 1.250s 378.762us 1 1 100.00
adc_ctrl_csr_aliasing 2.400s 799.074us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.560s 4408.229us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 7.800s 3674.078us 1 1 100.00
adc_ctrl_tl_intg_err 3.450s 11192.886us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 3.450s 11192.886us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.130s 791.876us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 64800059213564167234632922779266752726239723280428235257468513897022707693421 389
UVM_INFO @ 324244107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 55497404678901134785676634219151002777607644877030384820694933112911571833231 389
UVM_INFO @ 309666729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 46120875705985638279322056392772245261802112147010854692106511086229741854760 389
UVM_INFO @ 345417213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 103677281638154860745360115928433969953315439432321658853137797288117815442728 389
UVM_INFO @ 276668570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 111884191501073865646383893254493234336390716935334022519992722609891283067608 389
UVM_INFO @ 328117382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 24093982594362469342293324716648272732898504287493291793049658326016507238784 389
UVM_INFO @ 354393912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 58540342431391700717064100265474900622863385507887590856673073980610557394092 389
UVM_INFO @ 355984148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 67937393348482942037958353817347724125245076112319669223594796543929240551161 389
UVM_INFO @ 516304859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 55812913821102165920562625550472624654947526743161883293656047827729469555504 395
UVM_INFO @ 791875780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 98703812570503398274575407559940066923615385020289870569803547682539237099289 417
UVM_INFO @ 133880273244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---