Simulation Results: aes/masked

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.67 %
  • code
  • 95.19 %
  • assert
  • 98.14 %
  • func
  • 66.67 %
  • block
  • 95.63 %
  • line
  • 97.37 %
  • branch
  • 89.22 %
  • toggle
  • 98.05 %
  • FSM
  • 96.13 %
Validation stages
V1
100.00%
V2
94.74%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 140.428us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 61.604us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 95.058us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 57.284us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 292.293us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 335.586us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 57.831us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 57.284us 1 1 100.00
aes_csr_aliasing 2.000s 335.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 61.604us 1 1 100.00
aes_config_error 3.000s 145.238us 1 1 100.00
aes_stress 4.000s 142.408us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 61.604us 1 1 100.00
aes_config_error 3.000s 145.238us 1 1 100.00
aes_stress 4.000s 142.408us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 142.408us 1 1 100.00
aes_b2b 15.000s 759.537us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 142.408us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 61.604us 1 1 100.00
aes_config_error 3.000s 145.238us 1 1 100.00
aes_stress 4.000s 142.408us 1 1 100.00
aes_alert_reset 11.000s 10031.394us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 66.509us 1 1 100.00
aes_config_error 3.000s 145.238us 1 1 100.00
aes_alert_reset 11.000s 10031.394us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 5.000s 200.541us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 9.000s 198.227us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 307.978us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 11.000s 10031.394us 0 1 0.00
stress 1 1 100.00
aes_stress 4.000s 142.408us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 142.408us 1 1 100.00
aes_sideload 5.000s 101.110us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 184.087us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 31.000s 2760.174us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 146.728us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 96.977us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 116.124us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 116.124us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 95.058us 1 1 100.00
aes_csr_rw 2.000s 57.284us 1 1 100.00
aes_csr_aliasing 2.000s 335.586us 1 1 100.00
aes_same_csr_outstanding 3.000s 107.390us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 95.058us 1 1 100.00
aes_csr_rw 2.000s 57.284us 1 1 100.00
aes_csr_aliasing 2.000s 335.586us 1 1 100.00
aes_same_csr_outstanding 3.000s 107.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 520.978us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 56.000s 10008.159us 0 1 0.00
aes_control_fi 2.000s 49.669us 1 1 100.00
aes_cipher_fi 19.000s 10012.559us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 132.246us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 132.246us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 132.246us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 132.246us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 599.680us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 888.691us 1 1 100.00
aes_tl_intg_err 3.000s 135.598us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 135.598us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 11.000s 10031.394us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 132.246us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 132.246us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 61.604us 1 1 100.00
aes_stress 4.000s 142.408us 1 1 100.00
aes_alert_reset 11.000s 10031.394us 0 1 0.00
aes_core_fi 5.000s 465.718us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 146.728us 1 1 100.00
aes_config_error 3.000s 145.238us 1 1 100.00
aes_stress 4.000s 142.408us 1 1 100.00
aes_core_fi 5.000s 465.718us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 132.246us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 149.637us 1 1 100.00
aes_stress 4.000s 142.408us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 142.408us 1 1 100.00
aes_sideload 5.000s 101.110us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 149.637us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 149.637us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 149.637us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 149.637us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 149.637us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 142.408us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 142.408us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 56.000s 10008.159us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 56.000s 10008.159us 0 1 0.00
aes_control_fi 2.000s 49.669us 1 1 100.00
aes_cipher_fi 19.000s 10012.559us 0 1 0.00
aes_ctr_fi 2.000s 87.273us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 56.000s 10008.159us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 56.000s 10008.159us 0 1 0.00
aes_control_fi 2.000s 49.669us 1 1 100.00
aes_cipher_fi 19.000s 10012.559us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 19.000s 10012.559us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 56.000s 10008.159us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 56.000s 10008.159us 0 1 0.00
aes_control_fi 2.000s 49.669us 1 1 100.00
aes_ctr_fi 2.000s 87.273us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 56.000s 10008.159us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 56.000s 10008.159us 0 1 0.00
aes_control_fi 2.000s 49.669us 1 1 100.00
aes_cipher_fi 19.000s 10012.559us 0 1 0.00
aes_ctr_fi 2.000s 87.273us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 11.000s 10031.394us 0 1 0.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 56.000s 10008.159us 0 1 0.00
aes_control_fi 2.000s 49.669us 1 1 100.00
aes_cipher_fi 19.000s 10012.559us 0 1 0.00
aes_ctr_fi 2.000s 87.273us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 56.000s 10008.159us 0 1 0.00
aes_control_fi 2.000s 49.669us 1 1 100.00
aes_cipher_fi 19.000s 10012.559us 0 1 0.00
aes_ctr_fi 2.000s 87.273us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 56.000s 10008.159us 0 1 0.00
aes_control_fi 2.000s 49.669us 1 1 100.00
aes_ctr_fi 2.000s 87.273us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 56.000s 10008.159us 0 1 0.00
aes_ghash_fi 2.000s 108.212us 1 1 100.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 56.000s 10008.159us 0 1 0.00
aes_control_fi 2.000s 49.669us 1 1 100.00
aes_cipher_fi 19.000s 10012.559us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 16.000s 548.047us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred! 1 test run
aes_alert_reset 29318730138237431697167391228141723539537370083754599032972652512100397714355 469
UVM_INFO @ 10031394252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred! 1 test run
aes_fi 11885355428473701701517135843892951113007680166459919000121338509220085890793 2550
UVM_INFO @ 10008159332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 62670001416528074896680734648054896022708756770230094133098583454092334635234 141
UVM_INFO @ 10012559142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:306) virtual_sequencer [aes_alert_reset_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG 1 test run
aes_stress_all_with_rand_reset 86131205580436259105562002300842459105590117629032336077387038897497201324228 578
UVM_INFO @ 548046617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---