Simulation Results: aes/unmasked

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.72 %
  • code
  • 91.61 %
  • assert
  • 97.75 %
  • func
  • 64.80 %
  • block
  • 90.99 %
  • line
  • 93.15 %
  • branch
  • 83.82 %
  • toggle
  • 97.99 %
  • FSM
  • 91.49 %
Validation stages
V1
100.00%
V2
89.47%
V2S
77.78%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 84.637us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 106.844us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 386.596us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 70.074us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 465.532us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 228.404us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 434.199us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 70.074us 1 1 100.00
aes_csr_aliasing 2.000s 228.404us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 106.844us 1 1 100.00
aes_config_error 2.000s 92.505us 1 1 100.00
aes_stress 1.000s 103.905us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 106.844us 1 1 100.00
aes_config_error 2.000s 92.505us 1 1 100.00
aes_stress 1.000s 103.905us 1 1 100.00
back2back 2 2 100.00
aes_stress 1.000s 103.905us 1 1 100.00
aes_b2b 4.000s 88.980us 1 1 100.00
backpressure 1 1 100.00
aes_stress 1.000s 103.905us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 106.844us 1 1 100.00
aes_config_error 2.000s 92.505us 1 1 100.00
aes_stress 1.000s 103.905us 1 1 100.00
aes_alert_reset 30.000s 10007.703us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 1.000s 71.637us 1 1 100.00
aes_config_error 2.000s 92.505us 1 1 100.00
aes_alert_reset 30.000s 10007.703us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 178.913us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 708.136us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 1243.767us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 30.000s 10007.703us 0 1 0.00
stress 1 1 100.00
aes_stress 1.000s 103.905us 1 1 100.00
sideload 2 2 100.00
aes_stress 1.000s 103.905us 1 1 100.00
aes_sideload 2.000s 78.941us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 72.113us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 17.000s 10026.433us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 102.851us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 70.437us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 137.263us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 137.263us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 386.596us 1 1 100.00
aes_csr_rw 1.000s 70.074us 1 1 100.00
aes_csr_aliasing 2.000s 228.404us 1 1 100.00
aes_same_csr_outstanding 2.000s 244.771us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 386.596us 1 1 100.00
aes_csr_rw 1.000s 70.074us 1 1 100.00
aes_csr_aliasing 2.000s 228.404us 1 1 100.00
aes_same_csr_outstanding 2.000s 244.771us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 224.553us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 30.000s 10020.733us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 1.000s 47.637us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 261.775us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 261.775us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 261.775us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 261.775us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 326.172us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 10.000s 2523.321us 1 1 100.00
aes_tl_intg_err 2.000s 209.670us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 209.670us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 30.000s 10007.703us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 261.775us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 261.775us 1 1 100.00
sec_cm_main_config_sparse 2 4 50.00
aes_smoke 3.000s 106.844us 1 1 100.00
aes_stress 1.000s 103.905us 1 1 100.00
aes_alert_reset 30.000s 10007.703us 0 1 0.00
aes_core_fi 7.000s 10057.634us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 2.000s 102.851us 1 1 100.00
aes_config_error 2.000s 92.505us 1 1 100.00
aes_stress 1.000s 103.905us 1 1 100.00
aes_core_fi 7.000s 10057.634us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 261.775us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 58.360us 1 1 100.00
aes_stress 1.000s 103.905us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 1.000s 103.905us 1 1 100.00
aes_sideload 2.000s 78.941us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 58.360us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 58.360us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 58.360us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 58.360us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 58.360us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 1.000s 103.905us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 1.000s 103.905us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 30.000s 10020.733us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 30.000s 10020.733us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 1.000s 47.637us 1 1 100.00
aes_ctr_fi 2.000s 59.449us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 30.000s 10020.733us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 30.000s 10020.733us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 1.000s 47.637us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 47.637us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 30.000s 10020.733us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 30.000s 10020.733us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 59.449us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 30.000s 10020.733us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 30.000s 10020.733us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 1.000s 47.637us 1 1 100.00
aes_ctr_fi 2.000s 59.449us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 30.000s 10007.703us 0 1 0.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 30.000s 10020.733us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 1.000s 47.637us 1 1 100.00
aes_ctr_fi 2.000s 59.449us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 30.000s 10020.733us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 1.000s 47.637us 1 1 100.00
aes_ctr_fi 2.000s 59.449us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 30.000s 10020.733us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 59.449us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 30.000s 10020.733us 0 1 0.00
aes_ghash_fi 2.000s 50.969us 1 1 100.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 30.000s 10020.733us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 1.000s 47.637us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 21.000s 4008.050us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred! 2 test runs
aes_alert_reset 3189340268251737257250247470314783905181975065839272393236062408335251792685 523
UVM_INFO @ 10007702764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 113935154495118648940735065671414669442495262989977255077222221586290127713031 876
UVM_INFO @ 10026433149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred! 1 test run
aes_fi 32402640907302755430779169269252727096282192991843731848449645668543050435738 1209
UVM_INFO @ 10020733487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
aes_control_fi 8949551883481355915148365219407445139772075486175617379429802066556153438374 None
UVM_FATAL (cip_base_vseq.sv:454) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 113476229953785900333208582640029451737813581227336722186685200768707747845316 141
UVM_INFO @ 10057634255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
aes_stress_all_with_rand_reset 7358594529778362335879314124458272901847539458801372071470934699131011932972 950
UVM_INFO @ 4008049866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---