Simulation Results: chip

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.64 %
  • code
  • 84.97 %
  • assert
  • 97.37 %
  • func
  • 44.59 %
  • line
  • 94.33 %
  • branch
  • 93.55 %
  • cond
  • 88.58 %
  • toggle
  • 91.23 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
77.70%
V2S
100.00%
V3
65.38%
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 163.550s 3167.734us 1 1 100.00
chip_sw_example_rom 65.210s 2133.283us 1 1 100.00
chip_sw_example_manufacturer 143.590s 2708.139us 1 1 100.00
chip_sw_example_concurrency 193.900s 3113.097us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 169.180s 4697.670us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 224.160s 3873.476us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 474.920s 5924.863us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3257.970s 29989.320us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 54.680s 2111.677us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3257.970s 29989.320us 1 1 100.00
chip_csr_rw 224.160s 3873.476us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 4.600s 48.350us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 241.750s 3632.369us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 241.750s 3632.369us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 241.750s 3632.369us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 308.380s 3913.643us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 308.380s 3913.643us 1 1 100.00
chip_sw_uart_tx_rx_idx1 307.960s 3837.751us 1 1 100.00
chip_sw_uart_tx_rx_idx2 307.130s 4612.007us 1 1 100.00
chip_sw_uart_tx_rx_idx3 346.660s 4650.994us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 315.690s 4199.213us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 909.690s 8020.538us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 264.460s 4892.467us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 199.680s 4928.634us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 199.680s 4928.634us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 191.260s 3713.329us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 268.560s 6581.691us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 178.430s 4441.911us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 143.560s 3351.759us 1 1 100.00
chip_tap_straps_testunlock0 106.250s 3416.449us 1 1 100.00
chip_tap_straps_rma 221.890s 5111.765us 1 1 100.00
chip_tap_straps_prod 595.850s 10152.343us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 177.700s 3644.399us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 743.630s 8439.189us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 482.350s 5839.000us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 482.350s 5839.000us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 554.990s 7881.384us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1351.190s 13641.214us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 293.510s 3538.218us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 573.180s 5905.644us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3579.800s 19035.631us 1 1 100.00
chip_sw_aes_enc_jitter_en 200.760s 3561.554us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 546.790s 7381.109us 1 1 100.00
chip_sw_hmac_enc_jitter_en 143.240s 2509.883us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 812.720s 7863.359us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 162.070s 3366.907us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 295.410s 4242.918us 1 1 100.00
chip_sw_clkmgr_jitter 114.330s 2861.106us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 165.230s 3284.114us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 367.100s 6727.561us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 212.170s 4364.595us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 148.030s 3357.074us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 212.170s 4364.595us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 143.350s 3466.384us 1 1 100.00
chip_sw_aes_smoketest 169.800s 2847.625us 1 1 100.00
chip_sw_aon_timer_smoketest 167.530s 2457.089us 1 1 100.00
chip_sw_clkmgr_smoketest 156.700s 2488.164us 1 1 100.00
chip_sw_csrng_smoketest 166.240s 3363.639us 1 1 100.00
chip_sw_entropy_src_smoketest 769.500s 7233.264us 1 1 100.00
chip_sw_gpio_smoketest 211.470s 3224.752us 1 1 100.00
chip_sw_hmac_smoketest 151.650s 3132.236us 1 1 100.00
chip_sw_kmac_smoketest 182.620s 2984.805us 1 1 100.00
chip_sw_otbn_smoketest 622.030s 6118.076us 1 1 100.00
chip_sw_pwrmgr_smoketest 229.960s 5744.522us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 232.090s 5207.243us 1 1 100.00
chip_sw_rv_plic_smoketest 124.550s 2698.554us 1 1 100.00
chip_sw_rv_timer_smoketest 169.240s 2776.651us 1 1 100.00
chip_sw_rstmgr_smoketest 155.310s 3360.691us 1 1 100.00
chip_sw_sram_ctrl_smoketest 120.690s 2522.128us 1 1 100.00
chip_sw_uart_smoketest 138.300s 2613.097us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 149.460s 2777.527us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 286.690s 5470.367us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8175.450s 63656.207us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3003.260s 15940.850us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 34.989s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 177.840s 3098.520us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 155.010s 3047.485us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6879.380s 56001.243us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7487.710s 58575.369us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 61.220s 2835.078us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 61.220s 2835.078us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3257.970s 29989.320us 1 1 100.00
chip_same_csr_outstanding 1545.190s 16727.905us 1 1 100.00
chip_csr_hw_reset 169.180s 4697.670us 1 1 100.00
chip_csr_rw 224.160s 3873.476us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3257.970s 29989.320us 1 1 100.00
chip_same_csr_outstanding 1545.190s 16727.905us 1 1 100.00
chip_csr_hw_reset 169.180s 4697.670us 1 1 100.00
chip_csr_rw 224.160s 3873.476us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 25.680s 424.474us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.590s 49.333us 1 1 100.00
xbar_smoke_large_delays 45.120s 7961.675us 1 1 100.00
xbar_smoke_slow_rsp 40.360s 4669.136us 1 1 100.00
xbar_random_zero_delays 16.170s 209.752us 1 1 100.00
xbar_random_large_delays 337.630s 58194.873us 1 1 100.00
xbar_random_slow_rsp 237.770s 28407.893us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 21.310s 266.812us 1 1 100.00
xbar_error_and_unmapped_addr 17.230s 547.922us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 33.690s 1545.075us 1 1 100.00
xbar_error_and_unmapped_addr 17.230s 547.922us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 43.160s 1624.607us 1 1 100.00
xbar_access_same_device_slow_rsp 543.030s 61434.745us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 20.340s 370.382us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 60.700s 2475.476us 1 1 100.00
xbar_stress_all_with_error 162.920s 3501.875us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 169.090s 2655.386us 1 1 100.00
xbar_stress_all_with_reset_error 324.240s 12256.788us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3003.260s 15940.850us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2444.640s 27771.770us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2767.930s 15178.890us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 238.512s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 25.967s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 24.901s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 20.808s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 26.569s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 121.380s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 16.639s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 32.855s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 17.437s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 83.937s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 63.744s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 142.652s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 86.509s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 27.381s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 46.646s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 18.240s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 18.830s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 17.890s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 18.770s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 19.850s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 17.200s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 18.850s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 18.920s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 17.840s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 17.200s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 15.960s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 17.140s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 18.870s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 17.150s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 17.860s 10.140us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 246.696s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 74.824s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 162.289s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 66.067s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 61.956s 0.000us 0 1 0.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 5408.310s 29635.429us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 2847.220s 18397.695us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5775.500s 29132.903us 1 1 100.00
rom_e2e_static_critical 0 1 0.00
rom_e2e_static_critical 108.260s 2728.683us 0 1 0.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3090.070s 34806.889us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3090.070s 34806.889us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 131.600s 2154.159us 1 1 100.00
chip_sw_aes_enc_jitter_en 200.760s 3561.554us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 176.430s 2623.002us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 131.330s 2470.432us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 608.170s 6740.883us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 181.170s 3479.899us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 275.570s 4870.063us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 463.920s 6368.293us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 544.320s 5272.351us 1 1 100.00
chip_plic_all_irqs_10 234.050s 3161.297us 1 1 100.00
chip_plic_all_irqs_20 388.290s 4656.625us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 198.800s 3355.015us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1034.380s 11599.635us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 362.850s 5880.548us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 109.180s 2700.912us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.139s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 827.660s 8070.648us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 705.110s 6523.321us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 796.720s 8383.072us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 7403.260s 254777.820us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 251.310s 3940.741us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 229.960s 5744.522us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 251.310s 3940.741us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 367.220s 8406.382us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 367.220s 8406.382us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 331.840s 7472.689us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 444.650s 5895.738us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 536.590s 5482.376us 1 1 100.00
chip_sw_aes_idle 131.330s 2470.432us 1 1 100.00
chip_sw_hmac_enc_idle 153.130s 3221.663us 1 1 100.00
chip_sw_kmac_idle 176.770s 3642.793us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 292.940s 4819.146us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 355.240s 4937.385us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 291.810s 4304.549us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 238.430s 4480.029us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 957.150s 13405.733us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 397.050s 4311.405us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 369.010s 4456.784us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 362.080s 3913.171us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 334.730s 4044.014us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 414.690s 3879.595us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 351.460s 4663.819us 1 1 100.00
chip_sw_ast_clk_outputs 554.990s 7881.384us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 488.350s 13678.146us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 362.080s 3913.171us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 334.730s 4044.014us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 293.510s 3538.218us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 573.180s 5905.644us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3579.800s 19035.631us 1 1 100.00
chip_sw_aes_enc_jitter_en 200.760s 3561.554us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 546.790s 7381.109us 1 1 100.00
chip_sw_hmac_enc_jitter_en 143.240s 2509.883us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 812.720s 7863.359us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 162.070s 3366.907us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 295.410s 4242.918us 1 1 100.00
chip_sw_clkmgr_jitter 114.330s 2861.106us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 131.560s 3035.533us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 300.430s 4246.738us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 614.520s 7597.614us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3763.130s 25459.700us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 171.540s 3212.937us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 168.810s 3061.815us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1092.470s 12892.844us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 155.580s 3246.416us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 342.320s 5824.637us 1 1 100.00
chip_sw_flash_init_reduced_freq 1129.580s 23836.350us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 7549.520s 74694.548us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 554.990s 7881.384us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 390.610s 5134.112us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 246.750s 3575.469us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 463.920s 6368.293us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 827.660s 8070.648us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1761.160s 24618.344us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 156.910s 2718.013us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 410.100s 7555.988us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 137.970s 2982.538us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2404.710s 15379.859us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 177.870s 2996.144us 1 1 100.00
chip_sw_edn_entropy_reqs 797.760s 8119.353us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 177.870s 2996.144us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1761.160s 24618.344us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 135.380s 2813.730us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 940.200s 18693.789us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 496.330s 5540.252us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 573.180s 5905.644us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 359.210s 4777.411us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 293.510s 3538.218us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 2997.180s 43429.008us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 940.200s 18693.789us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 200.880s 3417.861us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1249.900s 10420.164us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 130.540s 3322.312us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 2997.180s 43429.008us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 130.540s 3322.312us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 130.540s 3322.312us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 130.540s 3322.312us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 130.540s 3322.312us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 463.920s 6368.293us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 73.040s 3591.807us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 503.220s 5336.910us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 407.240s 5741.897us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 407.240s 5741.897us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 167.600s 2748.309us 1 1 100.00
chip_sw_hmac_enc_jitter_en 143.240s 2509.883us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 153.130s 3221.663us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1332.790s 11406.821us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 622.390s 6109.146us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 421.880s 5021.114us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 378.580s 5600.552us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 408.930s 6051.805us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 320.000s 5166.614us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1249.900s 10420.164us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 812.720s 7863.359us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1691.290s 13202.310us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 608.170s 6740.883us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2953.190s 16948.034us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 157.790s 2834.516us 1 1 100.00
chip_sw_kmac_mode_kmac 196.960s 3023.738us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 162.070s 3366.907us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1249.900s 10420.164us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 522.960s 12295.300us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 115.590s 2860.846us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 577.540s 5685.223us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 176.770s 3642.793us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 275.570s 4870.063us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 143.560s 3351.759us 1 1 100.00
chip_tap_straps_rma 221.890s 5111.765us 1 1 100.00
chip_tap_straps_prod 595.850s 10152.343us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 135.650s 2457.603us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 522.960s 12295.300us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 522.960s 12295.300us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 522.960s 12295.300us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1348.170s 10479.720us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 130.540s 3322.312us 0 1 0.00
chip_sw_flash_rma_unlocked 2997.180s 43429.008us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 206.000s 3812.876us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 605.120s 8365.332us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 515.010s 6162.422us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 511.520s 6730.824us 0 1 0.00
chip_sw_lc_ctrl_transition 522.960s 12295.300us 1 1 100.00
chip_sw_keymgr_key_derivation 1249.900s 10420.164us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 334.670s 9520.782us 1 1 100.00
chip_sw_sram_ctrl_execution_main 490.630s 9444.060us 1 1 100.00
chip_prim_tl_access 73.040s 3591.807us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 488.350s 13678.146us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 397.050s 4311.405us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 369.010s 4456.784us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 362.080s 3913.171us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 334.730s 4044.014us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 414.690s 3879.595us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 351.460s 4663.819us 1 1 100.00
chip_tap_straps_dev 143.560s 3351.759us 1 1 100.00
chip_tap_straps_rma 221.890s 5111.765us 1 1 100.00
chip_tap_straps_prod 595.850s 10152.343us 1 1 100.00
chip_rv_dm_lc_disabled 49.940s 2014.104us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 201.850s 4397.177us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 72.110s 2958.412us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 87.950s 3013.694us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 188.220s 3713.335us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1445.920s 29383.707us 1 1 100.00
chip_rv_dm_lc_disabled 49.940s 2014.104us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 671.780s 10672.213us 0 1 0.00
chip_sw_lc_walkthrough_prod 569.820s 9604.259us 0 1 0.00
chip_sw_lc_walkthrough_prodend 557.300s 9363.663us 1 1 100.00
chip_sw_lc_walkthrough_rma 365.150s 7930.465us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1445.920s 29383.707us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 64.220s 2053.471us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 62.900s 2240.505us 1 1 100.00
rom_volatile_raw_unlock 103.804s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3534.770s 17622.446us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3579.800s 19035.631us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 536.590s 5482.376us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 536.590s 5482.376us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 536.590s 5482.376us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 297.630s 4143.179us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 522.960s 12295.300us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 940.200s 18693.789us 1 1 100.00
chip_sw_otbn_mem_scramble 297.630s 4143.179us 1 1 100.00
chip_sw_keymgr_key_derivation 1249.900s 10420.164us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 421.150s 5052.048us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 129.180s 3024.048us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 940.200s 18693.789us 1 1 100.00
chip_sw_otbn_mem_scramble 297.630s 4143.179us 1 1 100.00
chip_sw_keymgr_key_derivation 1249.900s 10420.164us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 421.150s 5052.048us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 129.180s 3024.048us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 522.960s 12295.300us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 365.420s 4739.113us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 135.650s 2457.603us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 206.000s 3812.876us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 605.120s 8365.332us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 515.010s 6162.422us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 511.520s 6730.824us 0 1 0.00
chip_sw_lc_ctrl_transition 522.960s 12295.300us 1 1 100.00
chip_prim_tl_access 73.040s 3591.807us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 73.040s 3591.807us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 793.890s 7480.368us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 60.680s 3127.641us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1017.280s 28476.417us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 273.570s 7748.665us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 401.780s 7443.179us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 380.380s 7667.728us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 986.450s 23485.042us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 417.850s 10006.404us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 367.220s 8406.382us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 593.180s 9931.957us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 295.680s 4951.433us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 60.680s 3127.641us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 188.520s 4285.134us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 2364.730s 32442.418us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 284.970s 7619.173us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 170.460s 2944.066us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 192.290s 5513.984us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 750.170s 8419.724us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 909.610s 11939.486us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1525.580s 29224.329us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 160.930s 3197.309us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 463.920s 6368.293us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 334.670s 9520.782us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 334.670s 9520.782us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 909.610s 11939.486us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 192.290s 5513.984us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 295.680s 4951.433us 1 1 100.00
chip_sw_pwrmgr_smoketest 229.960s 5744.522us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 287.670s 5262.640us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 402.700s 5576.669us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 322.980s 5060.768us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1034.380s 11599.635us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 187.200s 3583.103us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 463.920s 6368.293us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 705.110s 6523.321us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 470.340s 5300.441us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 472.060s 4829.207us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 162.640s 2469.334us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 129.180s 3024.048us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 402.700s 5576.669us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 402.700s 5576.669us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 571.250s 10999.418us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 930.830s 13668.826us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 287.670s 5262.640us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 162.240s 2918.032us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 318.550s 6026.910us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 221.890s 5111.765us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 49.940s 2014.104us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 544.320s 5272.351us 1 1 100.00
chip_plic_all_irqs_10 234.050s 3161.297us 1 1 100.00
chip_plic_all_irqs_20 388.290s 4656.625us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 165.520s 2821.965us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 186.010s 2954.230us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3003.260s 15940.850us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 417.320s 7318.066us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 240.150s 3760.398us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 222.570s 2934.602us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 169.670s 2855.510us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 421.150s 5052.048us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 295.410s 4242.918us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 388.220s 8645.514us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 358.050s 8977.535us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 490.630s 9444.060us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 463.920s 6368.293us 1 1 100.00
chip_sw_data_integrity_escalation 482.350s 5839.000us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 750.170s 8419.724us 1 1 100.00
chip_sw_sysrst_ctrl_reset 764.090s 22291.572us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 164.470s 3252.694us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 194.290s 3923.406us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 312.880s 4353.076us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 764.090s 22291.572us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 764.090s 22291.572us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2296.070s 20903.450us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2296.070s 20903.450us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 259.950s 6385.666us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3090.070s 34806.889us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 146.630s 3531.201us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 149.170s 3000.213us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 212.300s 3825.593us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 335.610s 4301.441us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 874.290s 8148.556us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4981.980s 31484.825us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1777.640s 11954.259us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 164.970s 3356.348us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 164.040s 3344.203us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 84.660s 2193.782us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9578.780s 71123.469us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 990.510s 6408.592us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 182.590s 3872.266us 0 1 0.00
rom_e2e_jtag_debug_dev 370.140s 6984.273us 0 1 0.00
rom_e2e_jtag_debug_rma 424.010s 6344.885us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 59.940s 2341.012us 0 1 0.00
rom_e2e_jtag_inject_dev 77.400s 2533.677us 0 1 0.00
rom_e2e_jtag_inject_rma 87.620s 2974.670us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 122.500s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 259.030s 3717.443us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 302.130s 3295.651us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 453.400s 4194.784us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 730.740s 6844.397us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 243.070s 3027.515us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 574.320s 6150.570us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 148.440s 3003.209us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 191.180s 3866.030us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 202.790s 5270.428us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 362.620s 4865.975us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 909.610s 11939.486us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 182.590s 3872.266us 0 1 0.00
rom_e2e_jtag_debug_dev 370.140s 6984.273us 0 1 0.00
rom_e2e_jtag_debug_rma 424.010s 6344.885us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 369.350s 4576.456us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 463.920s 6368.293us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5230.580s 38005.388us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5230.580s 38005.388us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 178.120s 3556.478us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 308.380s 3913.643us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2971.870s 18639.695us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 10 80.00
chip_sival_flash_info_access 201.630s 3168.110us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 405.270s 5046.484us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 4.870s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 188.960s 3406.059us 1 1 100.00
chip_sw_otp_ctrl_descrambling 187.440s 2616.695us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 234.200s 4325.040us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.134s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 179.470s 3830.480us 1 1 100.00
ate_bootstrap_flash_erase 6516.560s 44549.200us 1 1 100.00
ate_bootstrap_disjoint 9414.510s 84096.874us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 86721018261540805379761601326889972421523713485603434838420602332301160857838 None
---- STDERR ----
Another command (pid=2080440) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 37918583450393240935400230354308521719533659264567444388705948302961641883511 None
Another command (pid=753262) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=767339) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=788414) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 50281374875083597286104716421349782626909651269701431708617690764714660835620 None
Another command (pid=530050) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=555815) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=573679) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 62675360868671564748425799669069373230757311646583004668126142234310206770991 None
Another command (pid=555815) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=573679) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=570894) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 110829271046866593543109029395714694220555101080975206011023206769936424981040 None
Another command (pid=510151) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=545056) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=544705) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 46112502496220922967268615515389017663272966988555678075092547502197957515732 None
Another command (pid=576318) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=575018) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=424123) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 30444657935257999580941884057008040149218839248782126992393363708066785826444 None
Another command (pid=435606) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=422025) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=436712) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 42311068776020229406859220489215948060889036251829699383882957817229826843301 None
Another command (pid=422025) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=436712) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=368431) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 84671356243237967907996046319506029387661534642677301219543452571433288954093 None
Another command (pid=547413) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=579180) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=582879) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 44282554342971721999870766183588493535435206402811914706084557168555776703701 None
Another command (pid=528149) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=543902) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=510151) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 104907243292087557861174229854821985002650200243861928445798327311873492716958 None
Another command (pid=686083) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=693631) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=701085) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 110185118937983138625111011151387410971550639346375605514348282155714450085936 None
---- STDERR ----
Another command (pid=351043) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 5610430039874609412311866994633071821884453389944160515839436752512670567625 None
Another command (pid=696871) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=730744) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=736298) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 114071043396738831498217704248430219795994416909542501959585835145177262285766 None
Another command (pid=630719) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=557217) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=619391) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 77439609304112627731469557993162509291197471330992233023641012956851648430447 None
Another command (pid=496424) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=407255) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=448520) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 27916911539921033787882736939376900746270653015434749375169975848230937086089 None
Another command (pid=570894) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=563376) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=576318) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 13903424430705536925002225773478210255900073319418919850679441406637391716764 None
Another command (pid=720362) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=759815) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=780741) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 76398223190174556694566565657572039612596735975963057770356380889588211707384 None
Another command (pid=496424) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=526868) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=530595) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 14739752624960434011769512494781043726707912675697048683368651328267897279848 None
Another command (pid=594030) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=721516) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=722355) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 18183692801303664102172729229373822095347299483804362952837426039985999819489 None
Another command (pid=524916) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=496424) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=407255) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 103701588148649222038065153554976666028132291590373000184026955829143766980733 None
Another command (pid=422025) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=436712) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=378500) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 69276723864603788457042820765950996708507840252660609062957898418129272104464 None
Another command (pid=351043) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=422025) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=436712) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 17783988121926412644654789523463325467843146371634189734028376690725708028211 None
---- STDERR ----
Another command (pid=348101) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=402404) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 48608650298488732132662991376717832313818821651168241088290959351254432271201 None
Another command (pid=532340) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=523382) is running. Waiting for it to complete on the server (server_pid=237175)...
Another command (pid=354158) is running. Waiting for it to complete on the server (server_pid=237175)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 6 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 29296918956888559877175918548470076197505333611265266530262806779134236000748 332
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 53497281793218968630932343213816183958272681986889819469372033341266169148559 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 19245524291940431188685070447504845549799076328844711157143446018550912497482 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 55418833825831413078507585070352934288966163353694454323678431106924359616602 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 108799499103145289378307988007198993747497226918565271851463687939919987581542 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 958387064428584272089547173368056162648983579974995479670784892659576080025 312
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 34602731925818363385458529940266545241615445582375640784917473701737714068699 367
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 100249265248761699527362771027123024105798327769263728405374871407563691426773 364
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 51865969837585304161920248199538241762909358113730680010638641834419055009692 364
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 53175349270232304411171596449696267628633919366997159141627592622940577637678 327
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 15338268103931698307131938725341255543734175610535236641337769625126235855113 325
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 69992633808682557371326683331478652672746619714362185348119946739243814098424 326
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 1462757346868408185442312147249027820146579221501868535251242804336979708808 369
UVM_INFO @ 10672.213269 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 88650583477742680822746525633926730368727778016361124156133611296134420455137 369
UVM_INFO @ 9604.258632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 29067506921357579056806898424320555364650922646389683176100898148348908047713 341
UVM_INFO @ 7930.464712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 3 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 88968463404865568188669279234022423038178036127941974615363716682033816449262 320
UVM_ERROR @ 5513.984500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5513.984500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 105436724267442362783517319632547490021402429470816309332980716485212188939323 332
UVM_ERROR @ 10006.404000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 10006.404000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 4916979629105126110994448277287791034538672089465207511791568256170631668996 324
UVM_ERROR @ 8406.382000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8406.382000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 31369745116612024200342876630232832232652611768939545722421624891709422893195 328
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 97952703632972461898139869573535400728174005821136987564400218838008706743696 326
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 42529939195004596910962574223943933544024601589117332282509978420492691271577 328
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 2 test runs
chip_sw_otp_ctrl_escalation 30040583929628067007725020490339211758885661699456808301444332492346167314 321
UVM_ERROR @ 3866.029878 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3866.029878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 105423068010042892893212695291181116838939937063239118870413812913913788154260 312
UVM_ERROR @ 2718.013464 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2718.013464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 4260380264941018740433493589336449800514606049723823398116916831876621274202 222
TL item was: req: (cip_tl_seq_item@37759) { a_addr: 'h10428 a_data: 'h9fec9f3d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h199af d_param: 'h0 d_source: 'h23 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2835.078300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 48961642111892319344450193204297146020194379741382449239147488660796866565290 229
TL item was: req: (cip_tl_seq_item@31643) { a_addr: 'h10600 a_data: 'h971d90fb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he a_opcode: 'h4 a_user: 'h19eb1 d_param: 'h0 d_source: 'he d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2111.676811 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 5758233843968910841080882502891802988360277852843145125912754500066346606769 367
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 111694157824598718337226212898345517182200084853629587085530379003739788281063 326
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 6444376900210770361241399944123176841369389943515335156766659183454528316132 368
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 95679647073700547305148036460467175648267184557497205625625592064877654092920 326
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 49499067961284720712695552570812064399480414210917792109366036040227785547387 325
UVM_INFO @ 3760.397900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 49130002778851949096909134905624517021993689354888996331691566962348273208659 309
UVM_INFO @ 3322.311936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 17400406883847354641118848185770134225271333594068388106787745246669264106560 347
UVM_INFO @ 6730.824272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 113740294542123606381975320015362039334564226458749632433488314522263684117978 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 20636800546938948877220185666334896163348765682865526738234891396244274437190 308
UVM_ERROR @ 3127.640751 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 3127.640751 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 87256936019963182549230945769138676390534025632419216789190945016826579486590 318
UVM_ERROR @ 2944.066438 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2944.066438 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 64726713000766884653695918862933863143331613181360293055164345933032017497467 337
UVM_INFO @ 34806.888899 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 66607139050223319104212475923145090041856114544356438325324153749225003404560 307
UVM_INFO @ 3479.899254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 38650634270374863747392005927407920623226462199478623618994545088759725827406 308
UVM_INFO @ 2700.911758 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 72839997129366110837638844320982408630016391460526451619306175933060113134989 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 41541516347117800250380838303010891847850916450081622252440102901858378184208 348
UVM_INFO @ 3717.443249 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 36738796148363971561837289008414691577734469665139730595695424949867851270507 220
UVM_INFO @ 2014.103945 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_idle_load 62745616653974305100182110267491352497491178117637656610825960642424552559761 317
UVM_INFO @ 3098.520000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_sleep_load 64654884209287996613898040408813849526327208966479896931982322570195284100881 323
UVM_INFO @ 3047.485000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 28195489837136356117895000227847940264374697106536700385777038778105353977487 332
UVM_INFO @ 13641.214444 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 19765391869308939076588642406133539966908730550984266566837513891898660435045 325
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 48997484627929515386384520422536896151023309063309865673239696121719781554417 326
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds 1 test run
rom_e2e_jtag_debug_test_unlocked0 5435401306706350399839140679527106692750244938284168048455426372913632997435 318
UVM_INFO @ 3872.266030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)' 1 test run
rom_e2e_static_critical 64660936546883909466469092299034906406879968582913003076370931991661333461585 317
UVM_ERROR @ 2728.683480 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 2728.683480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_no_meas 80487646351903798070291669173281102027298535941773333785855304941069711723836 319
UVM_INFO @ 18397.695085 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 69499528592245485392681395307053344800476916512107599200394901713560432978729 332
UVM_ERROR @ 5470.367128 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5470.367128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---