Simulation Results: clkmgr

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.41 %
  • code
  • 98.37 %
  • assert
  • 95.76 %
  • func
  • 86.11 %
  • line
  • 99.01 %
  • branch
  • 98.62 %
  • cond
  • 95.02 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.830s 45.169us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.720s 18.840us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.870s 15.300us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.550s 397.439us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.070s 63.897us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.080s 33.832us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.870s 15.300us 1 1 100.00
clkmgr_csr_aliasing 1.070s 63.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.900s 115.205us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.690s 17.463us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.880s 58.332us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.790s 86.629us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.830s 45.169us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 2.830s 823.434us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 4.710s 1349.567us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 2.830s 823.434us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 27.310s 11363.167us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.010s 43.363us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.260s 49.824us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.260s 49.824us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.720s 18.840us 1 1 100.00
clkmgr_csr_rw 0.870s 15.300us 1 1 100.00
clkmgr_csr_aliasing 1.070s 63.897us 1 1 100.00
clkmgr_same_csr_outstanding 1.240s 62.874us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.720s 18.840us 1 1 100.00
clkmgr_csr_rw 0.870s 15.300us 1 1 100.00
clkmgr_csr_aliasing 1.070s 63.897us 1 1 100.00
clkmgr_same_csr_outstanding 1.240s 62.874us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.690s 1.723us 0 1 0.00
clkmgr_tl_intg_err 2.000s 357.477us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.440s 98.845us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.440s 98.845us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.440s 98.845us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.440s 98.845us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.090s 142.704us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.000s 357.477us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 2.830s 823.434us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 4.710s 1349.567us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.440s 98.845us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.870s 41.870us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.820s 28.292us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.930s 91.199us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.800s 21.983us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.910s 28.004us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.870s 15.300us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.690s 1.723us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.870s 15.300us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.870s 15.300us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.690s 1.723us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.930s 1063.711us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 39.070s 6833.878us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire 1 test run
clkmgr_sec_cm 4881751789795021375374534107282960711592883417854568510168452166551246843008 78
UVM_INFO @ 1723131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---