Simulation Results: edn/edn0

 
05/05/2026 15:30:24 DVSim: v1.34.0 sha: f7bfc3b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.15 %
  • code
  • 83.92 %
  • assert
  • 96.96 %
  • func
  • 80.56 %
  • line
  • 98.21 %
  • branch
  • 94.28 %
  • cond
  • 88.68 %
  • toggle
  • 84.67 %
  • FSM
  • 53.76 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.850s 18.197us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.870s 57.750us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.740s 22.848us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.350s 56.629us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.190s 94.663us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.960s 42.768us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.740s 22.848us 1 1 100.00
edn_csr_aliasing 1.190s 94.663us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.120s 70.183us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.120s 70.183us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.120s 70.183us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.950s 23.426us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.000s 75.541us 1 1 100.00
errs 1 1 100.00
edn_err 0.880s 22.834us 1 1 100.00
disable 2 2 100.00
edn_disable 0.880s 26.577us 1 1 100.00
edn_disable_auto_req_mode 0.930s 147.024us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.710s 250.602us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.730s 23.413us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.970s 15.870us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.560s 95.243us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.560s 95.243us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.870s 57.750us 1 1 100.00
edn_csr_rw 0.740s 22.848us 1 1 100.00
edn_csr_aliasing 1.190s 94.663us 1 1 100.00
edn_same_csr_outstanding 0.980s 34.690us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.870s 57.750us 1 1 100.00
edn_csr_rw 0.740s 22.848us 1 1 100.00
edn_csr_aliasing 1.190s 94.663us 1 1 100.00
edn_same_csr_outstanding 0.980s 34.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 8.570s 2290.429us 1 1 100.00
edn_tl_intg_err 1.200s 439.400us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.820s 61.731us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.000s 75.541us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.570s 2290.429us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.570s 2290.429us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 8.570s 2290.429us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 8.570s 2290.429us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.000s 75.541us 1 1 100.00
edn_sec_cm 8.570s 2290.429us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.000s 75.541us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.200s 439.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 46.300s 2989.192us 1 1 100.00